Updating Opus to release 1.1

silk/arm/macros_armv4.h

 /***********************************************************************
 Copyright (C) 2013 Xiph.Org Foundation and contributors.
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions
 are met:
 - Redistributions of source code must retain the above copyright notice,
 this list of conditions and the following disclaimer.
 - Redistributions in binary form must reproduce the above copyright
 notice, this list of conditions and the following disclaimer in the
 documentation and/or other materials provided with the distribution.
@@ skipping 12 matching lines @@
 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 POSSIBILITY OF SUCH DAMAGE.
 ***********************************************************************/
 
 #ifndef SILK_MACROS_ARMv4_H
 #define SILK_MACROS_ARMv4_H
 
 /* (a32 * (opus_int32)((opus_int16)(b32))) >> 16 output have to be 32bit int */
 #undef silk_SMULWB
-static inline opus_int32 silk_SMULWB_armv4(opus_int32 a, opus_int16 b)
+static OPUS_INLINE opus_int32 silk_SMULWB_armv4(opus_int32 a, opus_int16 b)
 {
   unsigned rd_lo;
   int rd_hi;
   __asm__(
       "#silk_SMULWB\n\t"
       "smull %0, %1, %2, %3\n\t"
       : "=&r"(rd_lo), "=&r"(rd_hi)
       : "%r"(a), "r"(b<<16)
   );
   return rd_hi;
 }
 #define silk_SMULWB(a, b) (silk_SMULWB_armv4(a, b))
 
 /* a32 + (b32 * (opus_int32)((opus_int16)(c32))) >> 16 output have to be 32bit int */
 #undef silk_SMLAWB
 #define silk_SMLAWB(a, b, c) ((a) + silk_SMULWB(b, c))
 
 /* (a32 * (b32 >> 16)) >> 16 */
 #undef silk_SMULWT
-static inline opus_int32 silk_SMULWT_armv4(opus_int32 a, opus_int32 b)
+static OPUS_INLINE opus_int32 silk_SMULWT_armv4(opus_int32 a, opus_int32 b)
 {
   unsigned rd_lo;
   int rd_hi;
   __asm__(
       "#silk_SMULWT\n\t"
       "smull %0, %1, %2, %3\n\t"
       : "=&r"(rd_lo), "=&r"(rd_hi)
       : "%r"(a), "r"(b&~0xFFFF)
   );
   return rd_hi;
 }
 #define silk_SMULWT(a, b) (silk_SMULWT_armv4(a, b))
 
 /* a32 + (b32 * (c32 >> 16)) >> 16 */
 #undef silk_SMLAWT
 #define silk_SMLAWT(a, b, c) ((a) + silk_SMULWT(b, c))
 
 /* (a32 * b32) >> 16 */
 #undef silk_SMULWW
-static inline opus_int32 silk_SMULWW_armv4(opus_int32 a, opus_int32 b)
+static OPUS_INLINE opus_int32 silk_SMULWW_armv4(opus_int32 a, opus_int32 b)
 {
   unsigned rd_lo;
   int rd_hi;
   __asm__(
     "#silk_SMULWW\n\t"
     "smull %0, %1, %2, %3\n\t"
     : "=&r"(rd_lo), "=&r"(rd_hi)
     : "%r"(a), "r"(b)
   );
   return (rd_hi<<16)+(rd_lo>>16);
 }
 #define silk_SMULWW(a, b) (silk_SMULWW_armv4(a, b))
 
 #undef silk_SMLAWW
-static inline opus_int32 silk_SMLAWW_armv4(opus_int32 a, opus_int32 b,
+static OPUS_INLINE opus_int32 silk_SMLAWW_armv4(opus_int32 a, opus_int32 b,
  opus_int32 c)
 {
   unsigned rd_lo;
   int rd_hi;
   __asm__(
     "#silk_SMLAWW\n\t"
     "smull %0, %1, %2, %3\n\t"
     : "=&r"(rd_lo), "=&r"(rd_hi)
     : "%r"(b), "r"(c)
   );
   return a+(rd_hi<<16)+(rd_lo>>16);
 }
 #define silk_SMLAWW(a, b, c) (silk_SMLAWW_armv4(a, b, c))
 
 #endif /* SILK_MACROS_ARMv4_H */