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| 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 // All Rights Reserved. | 2 // All Rights Reserved. |
| 3 // | 3 // |
| 4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
| 5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
| 6 // are met: | 6 // are met: |
| 7 // | 7 // |
| 8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
| 9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
| 10 // | 10 // |
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| 2658 void Assembler::vss(byte op, XMMRegister dst, XMMRegister src1, | 2658 void Assembler::vss(byte op, XMMRegister dst, XMMRegister src1, |
| 2659 const Operand& src2) { | 2659 const Operand& src2) { |
| 2660 DCHECK(IsEnabled(AVX)); | 2660 DCHECK(IsEnabled(AVX)); |
| 2661 EnsureSpace ensure_space(this); | 2661 EnsureSpace ensure_space(this); |
| 2662 emit_vex_prefix(src1, kLIG, kF3, k0F, kWIG); | 2662 emit_vex_prefix(src1, kLIG, kF3, k0F, kWIG); |
| 2663 EMIT(op); | 2663 EMIT(op); |
| 2664 emit_sse_operand(dst, src2); | 2664 emit_sse_operand(dst, src2); |
| 2665 } | 2665 } |
| 2666 | 2666 |
| 2667 | 2667 |
| 2668 void Assembler::vps(byte op, XMMRegister dst, XMMRegister src1, |
| 2669 const Operand& src2) { |
| 2670 DCHECK(IsEnabled(AVX)); |
| 2671 EnsureSpace ensure_space(this); |
| 2672 emit_vex_prefix(src1, kL128, kNone, k0F, kWIG); |
| 2673 EMIT(op); |
| 2674 emit_sse_operand(dst, src2); |
| 2675 } |
| 2676 |
| 2677 |
| 2678 void Assembler::vpd(byte op, XMMRegister dst, XMMRegister src1, |
| 2679 const Operand& src2) { |
| 2680 DCHECK(IsEnabled(AVX)); |
| 2681 EnsureSpace ensure_space(this); |
| 2682 emit_vex_prefix(src1, kL128, k66, k0F, kWIG); |
| 2683 EMIT(op); |
| 2684 emit_sse_operand(dst, src2); |
| 2685 } |
| 2686 |
| 2687 |
| 2668 void Assembler::bmi1(byte op, Register reg, Register vreg, const Operand& rm) { | 2688 void Assembler::bmi1(byte op, Register reg, Register vreg, const Operand& rm) { |
| 2669 DCHECK(IsEnabled(BMI1)); | 2689 DCHECK(IsEnabled(BMI1)); |
| 2670 EnsureSpace ensure_space(this); | 2690 EnsureSpace ensure_space(this); |
| 2671 emit_vex_prefix(vreg, kLZ, kNone, k0F38, kW0); | 2691 emit_vex_prefix(vreg, kLZ, kNone, k0F38, kW0); |
| 2672 EMIT(op); | 2692 EMIT(op); |
| 2673 emit_operand(reg, rm); | 2693 emit_operand(reg, rm); |
| 2674 } | 2694 } |
| 2675 | 2695 |
| 2676 | 2696 |
| 2677 void Assembler::tzcnt(Register dst, const Operand& src) { | 2697 void Assembler::tzcnt(Register dst, const Operand& src) { |
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| 2955 fprintf(coverage_log, "%s\n", file_line); | 2975 fprintf(coverage_log, "%s\n", file_line); |
| 2956 fflush(coverage_log); | 2976 fflush(coverage_log); |
| 2957 } | 2977 } |
| 2958 } | 2978 } |
| 2959 | 2979 |
| 2960 #endif | 2980 #endif |
| 2961 | 2981 |
| 2962 } } // namespace v8::internal | 2982 } } // namespace v8::internal |
| 2963 | 2983 |
| 2964 #endif // V8_TARGET_ARCH_IA32 | 2984 #endif // V8_TARGET_ARCH_IA32 |
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