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Side by Side Diff: src/ia32/assembler-ia32.h

Issue 10701054: Enable stub generation using Hydrogen/Lithium (again) (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: First pass at pre-VFP2 RA Created 8 years, 1 month ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are 5 // modification, are permitted provided that the following conditions are
6 // met: 6 // met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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58 // 58 //
59 // 3) By not using an enum, we are possibly preventing the compiler from 59 // 3) By not using an enum, we are possibly preventing the compiler from
60 // doing certain constant folds, which may significantly reduce the 60 // doing certain constant folds, which may significantly reduce the
61 // code generated for some assembly instructions (because they boil down 61 // code generated for some assembly instructions (because they boil down
62 // to a few constants). If this is a problem, we could change the code 62 // to a few constants). If this is a problem, we could change the code
63 // such that we use an enum in optimized mode, and the struct in debug 63 // such that we use an enum in optimized mode, and the struct in debug
64 // mode. This way we get the compile-time error checking in debug mode 64 // mode. This way we get the compile-time error checking in debug mode
65 // and best performance in optimized code. 65 // and best performance in optimized code.
66 // 66 //
67 struct Register { 67 struct Register {
68 static const int kNumAllocatableRegisters = 6; 68 static const int kMaxNumAllocatableRegisters = 6;
69 static int NumAllocatableRegisters() {
70 return kMaxNumAllocatableRegisters;
71 }
69 static const int kNumRegisters = 8; 72 static const int kNumRegisters = 8;
70 73
71 static inline const char* AllocationIndexToString(int index); 74 static inline const char* AllocationIndexToString(int index);
72 75
73 static inline int ToAllocationIndex(Register reg); 76 static inline int ToAllocationIndex(Register reg);
74 77
75 static inline Register FromAllocationIndex(int index); 78 static inline Register FromAllocationIndex(int index);
76 79
77 static Register from_code(int code) { 80 static Register from_code(int code) {
78 ASSERT(code >= 0); 81 ASSERT(code >= 0);
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112 const Register edx = { kRegister_edx_Code }; 115 const Register edx = { kRegister_edx_Code };
113 const Register ebx = { kRegister_ebx_Code }; 116 const Register ebx = { kRegister_ebx_Code };
114 const Register esp = { kRegister_esp_Code }; 117 const Register esp = { kRegister_esp_Code };
115 const Register ebp = { kRegister_ebp_Code }; 118 const Register ebp = { kRegister_ebp_Code };
116 const Register esi = { kRegister_esi_Code }; 119 const Register esi = { kRegister_esi_Code };
117 const Register edi = { kRegister_edi_Code }; 120 const Register edi = { kRegister_edi_Code };
118 const Register no_reg = { kRegister_no_reg_Code }; 121 const Register no_reg = { kRegister_no_reg_Code };
119 122
120 123
121 inline const char* Register::AllocationIndexToString(int index) { 124 inline const char* Register::AllocationIndexToString(int index) {
122 ASSERT(index >= 0 && index < kNumAllocatableRegisters); 125 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
123 // This is the mapping of allocation indices to registers. 126 // This is the mapping of allocation indices to registers.
124 const char* const kNames[] = { "eax", "ecx", "edx", "ebx", "esi", "edi" }; 127 const char* const kNames[] = { "eax", "ecx", "edx", "ebx", "esi", "edi" };
125 return kNames[index]; 128 return kNames[index];
126 } 129 }
127 130
128 131
129 inline int Register::ToAllocationIndex(Register reg) { 132 inline int Register::ToAllocationIndex(Register reg) {
130 ASSERT(reg.is_valid() && !reg.is(esp) && !reg.is(ebp)); 133 ASSERT(reg.is_valid() && !reg.is(esp) && !reg.is(ebp));
131 return (reg.code() >= 6) ? reg.code() - 2 : reg.code(); 134 return (reg.code() >= 6) ? reg.code() - 2 : reg.code();
132 } 135 }
133 136
134 137
135 inline Register Register::FromAllocationIndex(int index) { 138 inline Register Register::FromAllocationIndex(int index) {
136 ASSERT(index >= 0 && index < kNumAllocatableRegisters); 139 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
137 return (index >= 4) ? from_code(index + 2) : from_code(index); 140 return (index >= 4) ? from_code(index + 2) : from_code(index);
138 } 141 }
139 142
140 143
141 struct XMMRegister { 144 struct IntelDoubleRegister {
142 static const int kNumAllocatableRegisters = 7; 145 static const int kMaxNumAllocatableRegisters = 7;
143 static const int kNumRegisters = 8; 146 explicit IntelDoubleRegister(int code) { code_ = code; }
147 static int NumAllocatableRegisters();
148 static int NumRegisters();
149 static const char* AllocationIndexToString(int index);
144 150
145 static int ToAllocationIndex(XMMRegister reg) { 151 static int ToAllocationIndex(IntelDoubleRegister reg) {
146 ASSERT(reg.code() != 0); 152 ASSERT(reg.code() != 0);
147 return reg.code() - 1; 153 return reg.code() - 1;
148 } 154 }
149 155
150 static XMMRegister FromAllocationIndex(int index) { 156 static IntelDoubleRegister FromAllocationIndex(int index) {
151 ASSERT(index >= 0 && index < kNumAllocatableRegisters); 157 ASSERT(index >= 0 && index < NumAllocatableRegisters());
152 return from_code(index + 1); 158 return from_code(index + 1);
153 } 159 }
154 160
161 static IntelDoubleRegister from_code(int code) {
162 IntelDoubleRegister r = IntelDoubleRegister(code);
163 return r;
164 }
165
166 bool is_valid() const {
167 return 0 <= code_ && code_ < NumRegisters();
168 }
169 bool is(IntelDoubleRegister reg) const { return code_ == reg.code_; }
170 int code() const {
171 ASSERT(is_valid());
172 return code_;
173 }
174
175 int code_;
176 };
177
178 struct XMMRegister : IntelDoubleRegister {
179 static const int kNumAllocatableRegisters = 7;
180 static const int kNumRegisters = 8;
181
182 explicit XMMRegister(int code) : IntelDoubleRegister(code) {}
183
184 static XMMRegister from_code(int code) {
185 XMMRegister r = XMMRegister(code);
186 return r;
187 }
188
189 static XMMRegister FromAllocationIndex(int index) {
190 ASSERT(index >= 0 && index < NumAllocatableRegisters());
191 return from_code(index + 1);
192 }
193
155 static const char* AllocationIndexToString(int index) { 194 static const char* AllocationIndexToString(int index) {
156 ASSERT(index >= 0 && index < kNumAllocatableRegisters); 195 ASSERT(index >= 0 && index < kNumAllocatableRegisters);
157 const char* const names[] = { 196 const char* const names[] = {
158 "xmm1", 197 "xmm1",
159 "xmm2", 198 "xmm2",
160 "xmm3", 199 "xmm3",
161 "xmm4", 200 "xmm4",
162 "xmm5", 201 "xmm5",
163 "xmm6", 202 "xmm6",
164 "xmm7" 203 "xmm7"
165 }; 204 };
166 return names[index]; 205 return names[index];
167 } 206 }
168
169 static XMMRegister from_code(int code) {
170 XMMRegister r = { code };
171 return r;
172 }
173
174 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
175 bool is(XMMRegister reg) const { return code_ == reg.code_; }
176 int code() const {
177 ASSERT(is_valid());
178 return code_;
179 }
180
181 int code_;
182 }; 207 };
183 208
184 209
185 const XMMRegister xmm0 = { 0 }; 210 const XMMRegister xmm0 = XMMRegister(0);
186 const XMMRegister xmm1 = { 1 }; 211 const XMMRegister xmm1 = XMMRegister(1);
187 const XMMRegister xmm2 = { 2 }; 212 const XMMRegister xmm2 = XMMRegister(2);
188 const XMMRegister xmm3 = { 3 }; 213 const XMMRegister xmm3 = XMMRegister(3);
189 const XMMRegister xmm4 = { 4 }; 214 const XMMRegister xmm4 = XMMRegister(4);
190 const XMMRegister xmm5 = { 5 }; 215 const XMMRegister xmm5 = XMMRegister(5);
191 const XMMRegister xmm6 = { 6 }; 216 const XMMRegister xmm6 = XMMRegister(6);
192 const XMMRegister xmm7 = { 7 }; 217 const XMMRegister xmm7 = XMMRegister(7);
193 218
219 struct X87TopOfStackProxyRegister : IntelDoubleRegister {
Jakob Kummerow 2012/11/19 12:36:00 s/Proxy//
danno 2012/11/26 17:16:18 Done.
220 static const int kNumAllocatableRegisters = 1;
221 static const int kNumRegisters = 1;
194 222
195 typedef XMMRegister DoubleRegister; 223 explicit X87TopOfStackProxyRegister(int code)
224 : IntelDoubleRegister(code) {}
225
226 static const char* AllocationIndexToString(int index) {
227 ASSERT(index >= 0 && index < kNumAllocatableRegisters);
228 const char* const names[] = {
229 "st0",
230 };
231 return names[index];
232 }
233 static int ToAllocationIndex(X87TopOfStackProxyRegister reg) {
234 ASSERT(reg.code() == 0);
235 return 0;
236 }
237 };
238
239 const X87TopOfStackProxyRegister x87tos = X87TopOfStackProxyRegister(0);
240
241 typedef IntelDoubleRegister DoubleRegister;
196 242
197 243
198 enum Condition { 244 enum Condition {
199 // any value < 0 is considered no_condition 245 // any value < 0 is considered no_condition
200 no_condition = -1, 246 no_condition = -1,
201 247
202 overflow = 0, 248 overflow = 0,
203 no_overflow = 1, 249 no_overflow = 1,
204 below = 2, 250 below = 2,
205 above_equal = 3, 251 above_equal = 3,
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1216 private: 1262 private:
1217 Assembler* assembler_; 1263 Assembler* assembler_;
1218 #ifdef DEBUG 1264 #ifdef DEBUG
1219 int space_before_; 1265 int space_before_;
1220 #endif 1266 #endif
1221 }; 1267 };
1222 1268
1223 } } // namespace v8::internal 1269 } } // namespace v8::internal
1224 1270
1225 #endif // V8_IA32_ASSEMBLER_IA32_H_ 1271 #endif // V8_IA32_ASSEMBLER_IA32_H_
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