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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <assert.h> | 5 #include <assert.h> |
6 #include <stdarg.h> | 6 #include <stdarg.h> |
7 #include <stdio.h> | 7 #include <stdio.h> |
8 | 8 |
9 #include "src/v8.h" | 9 #include "src/v8.h" |
10 | 10 |
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292 KSHR = 5, | 292 KSHR = 5, |
293 kSAR = 7 | 293 kSAR = 7 |
294 }; | 294 }; |
295 | 295 |
296 bool vex_128() { | 296 bool vex_128() { |
297 DCHECK(vex_byte0_ == 0xc4 || vex_byte0_ == 0xc5); | 297 DCHECK(vex_byte0_ == 0xc4 || vex_byte0_ == 0xc5); |
298 byte checked = vex_byte0_ == 0xc4 ? vex_byte2_ : vex_byte1_; | 298 byte checked = vex_byte0_ == 0xc4 ? vex_byte2_ : vex_byte1_; |
299 return (checked & 4) != 1; | 299 return (checked & 4) != 1; |
300 } | 300 } |
301 | 301 |
| 302 bool vex_none() { |
| 303 DCHECK(vex_byte0_ == 0xc4 || vex_byte0_ == 0xc5); |
| 304 byte checked = vex_byte0_ == 0xc4 ? vex_byte2_ : vex_byte1_; |
| 305 return (checked & 3) == 0; |
| 306 } |
| 307 |
302 bool vex_66() { | 308 bool vex_66() { |
303 DCHECK(vex_byte0_ == 0xc4 || vex_byte0_ == 0xc5); | 309 DCHECK(vex_byte0_ == 0xc4 || vex_byte0_ == 0xc5); |
304 byte checked = vex_byte0_ == 0xc4 ? vex_byte2_ : vex_byte1_; | 310 byte checked = vex_byte0_ == 0xc4 ? vex_byte2_ : vex_byte1_; |
305 return (checked & 3) == 1; | 311 return (checked & 3) == 1; |
306 } | 312 } |
307 | 313 |
308 bool vex_f3() { | 314 bool vex_f3() { |
309 DCHECK(vex_byte0_ == 0xc4 || vex_byte0_ == 0xc5); | 315 DCHECK(vex_byte0_ == 0xc4 || vex_byte0_ == 0xc5); |
310 byte checked = vex_byte0_ == 0xc4 ? vex_byte2_ : vex_byte1_; | 316 byte checked = vex_byte0_ == 0xc4 ? vex_byte2_ : vex_byte1_; |
311 return (checked & 3) == 2; | 317 return (checked & 3) == 2; |
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797 case 0xaf: | 803 case 0xaf: |
798 AppendToBuffer("vfnmsub213s%c %s,%s,", float_size_code(), | 804 AppendToBuffer("vfnmsub213s%c %s,%s,", float_size_code(), |
799 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); | 805 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); |
800 current += PrintRightXMMOperand(current); | 806 current += PrintRightXMMOperand(current); |
801 break; | 807 break; |
802 case 0xbf: | 808 case 0xbf: |
803 AppendToBuffer("vfnmsub231s%c %s,%s,", float_size_code(), | 809 AppendToBuffer("vfnmsub231s%c %s,%s,", float_size_code(), |
804 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); | 810 NameOfXMMRegister(regop), NameOfXMMRegister(vvvv)); |
805 current += PrintRightXMMOperand(current); | 811 current += PrintRightXMMOperand(current); |
806 break; | 812 break; |
| 813 case 0xf7: |
| 814 AppendToBuffer("shlx %s,", NameOfCPURegister(regop)); |
| 815 current += PrintRightOperand(current); |
| 816 AppendToBuffer(",%s", NameOfCPURegister(vvvv)); |
| 817 break; |
807 default: | 818 default: |
808 UnimplementedInstruction(); | 819 UnimplementedInstruction(); |
809 } | 820 } |
810 } else if (vex_f2() && vex_0f()) { | 821 } else if (vex_f2() && vex_0f()) { |
811 int mod, regop, rm, vvvv = vex_vreg(); | 822 int mod, regop, rm, vvvv = vex_vreg(); |
812 get_modrm(*current, &mod, ®op, &rm); | 823 get_modrm(*current, &mod, ®op, &rm); |
813 switch (opcode) { | 824 switch (opcode) { |
814 case 0x58: | 825 case 0x58: |
815 AppendToBuffer("vaddsd %s,%s,", NameOfXMMRegister(regop), | 826 AppendToBuffer("vaddsd %s,%s,", NameOfXMMRegister(regop), |
816 NameOfXMMRegister(vvvv)); | 827 NameOfXMMRegister(vvvv)); |
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874 current += PrintRightXMMOperand(current); | 885 current += PrintRightXMMOperand(current); |
875 break; | 886 break; |
876 case 0x5f: | 887 case 0x5f: |
877 AppendToBuffer("vmaxss %s,%s,", NameOfXMMRegister(regop), | 888 AppendToBuffer("vmaxss %s,%s,", NameOfXMMRegister(regop), |
878 NameOfXMMRegister(vvvv)); | 889 NameOfXMMRegister(vvvv)); |
879 current += PrintRightXMMOperand(current); | 890 current += PrintRightXMMOperand(current); |
880 break; | 891 break; |
881 default: | 892 default: |
882 UnimplementedInstruction(); | 893 UnimplementedInstruction(); |
883 } | 894 } |
| 895 } else if (vex_none() && vex_0f38()) { |
| 896 int mod, regop, rm, vvvv = vex_vreg(); |
| 897 get_modrm(*current, &mod, ®op, &rm); |
| 898 const char* mnem = "?"; |
| 899 switch (opcode) { |
| 900 case 0xf2: |
| 901 AppendToBuffer("andn %s,%s,", NameOfCPURegister(regop), |
| 902 NameOfCPURegister(vvvv)); |
| 903 current += PrintRightOperand(current); |
| 904 break; |
| 905 case 0xf5: |
| 906 AppendToBuffer("bzhi %s,", NameOfCPURegister(regop)); |
| 907 current += PrintRightOperand(current); |
| 908 AppendToBuffer(",%s", NameOfCPURegister(vvvv)); |
| 909 break; |
| 910 case 0xf7: |
| 911 AppendToBuffer("bextr %s,", NameOfCPURegister(regop)); |
| 912 current += PrintRightOperand(current); |
| 913 AppendToBuffer(",%s", NameOfCPURegister(vvvv)); |
| 914 break; |
| 915 case 0xf3: |
| 916 switch (regop) { |
| 917 case 1: |
| 918 mnem = "blsr"; |
| 919 break; |
| 920 case 2: |
| 921 mnem = "blsmsk"; |
| 922 break; |
| 923 case 3: |
| 924 mnem = "blsi"; |
| 925 break; |
| 926 default: |
| 927 UnimplementedInstruction(); |
| 928 } |
| 929 AppendToBuffer("%s %s,", mnem, NameOfCPURegister(vvvv)); |
| 930 current += PrintRightOperand(current); |
| 931 mnem = "?"; |
| 932 break; |
| 933 default: |
| 934 UnimplementedInstruction(); |
| 935 } |
| 936 } else if (vex_f2() && vex_0f38()) { |
| 937 int mod, regop, rm, vvvv = vex_vreg(); |
| 938 get_modrm(*current, &mod, ®op, &rm); |
| 939 switch (opcode) { |
| 940 case 0xf5: |
| 941 AppendToBuffer("pdep %s,%s,", NameOfCPURegister(regop), |
| 942 NameOfCPURegister(vvvv)); |
| 943 current += PrintRightOperand(current); |
| 944 break; |
| 945 case 0xf6: |
| 946 AppendToBuffer("mulx %s,%s,", NameOfCPURegister(regop), |
| 947 NameOfCPURegister(vvvv)); |
| 948 current += PrintRightOperand(current); |
| 949 break; |
| 950 case 0xf7: |
| 951 AppendToBuffer("shrx %s,", NameOfCPURegister(regop)); |
| 952 current += PrintRightOperand(current); |
| 953 AppendToBuffer(",%s", NameOfCPURegister(vvvv)); |
| 954 break; |
| 955 default: |
| 956 UnimplementedInstruction(); |
| 957 } |
| 958 } else if (vex_f3() && vex_0f38()) { |
| 959 int mod, regop, rm, vvvv = vex_vreg(); |
| 960 get_modrm(*current, &mod, ®op, &rm); |
| 961 switch (opcode) { |
| 962 case 0xf5: |
| 963 AppendToBuffer("pext %s,%s,", NameOfCPURegister(regop), |
| 964 NameOfCPURegister(vvvv)); |
| 965 current += PrintRightOperand(current); |
| 966 break; |
| 967 case 0xf7: |
| 968 AppendToBuffer("sarx %s,", NameOfCPURegister(regop)); |
| 969 current += PrintRightOperand(current); |
| 970 AppendToBuffer(",%s", NameOfCPURegister(vvvv)); |
| 971 break; |
| 972 default: |
| 973 UnimplementedInstruction(); |
| 974 } |
| 975 } else if (vex_f2() && vex_0f3a()) { |
| 976 int mod, regop, rm; |
| 977 get_modrm(*current, &mod, ®op, &rm); |
| 978 switch (opcode) { |
| 979 case 0xf0: |
| 980 AppendToBuffer("rorx %s,", NameOfCPURegister(regop)); |
| 981 current += PrintRightOperand(current); |
| 982 AppendToBuffer(",%d", *current & 0x1f); |
| 983 current += 1; |
| 984 break; |
| 985 default: |
| 986 UnimplementedInstruction(); |
| 987 } |
884 } else { | 988 } else { |
885 UnimplementedInstruction(); | 989 UnimplementedInstruction(); |
886 } | 990 } |
887 | 991 |
888 return static_cast<int>(current - data); | 992 return static_cast<int>(current - data); |
889 } | 993 } |
890 | 994 |
891 | 995 |
892 // Returns number of bytes used, including *data. | 996 // Returns number of bytes used, including *data. |
893 int DisassemblerIA32::FPUInstruction(byte* data) { | 997 int DisassemblerIA32::FPUInstruction(byte* data) { |
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1893 get_modrm(*data, &mod, ®op, &rm); | 1997 get_modrm(*data, &mod, ®op, &rm); |
1894 AppendToBuffer("movdqu %s,", NameOfXMMRegister(regop)); | 1998 AppendToBuffer("movdqu %s,", NameOfXMMRegister(regop)); |
1895 data += PrintRightXMMOperand(data); | 1999 data += PrintRightXMMOperand(data); |
1896 } else if (b2 == 0x7F) { | 2000 } else if (b2 == 0x7F) { |
1897 AppendToBuffer("movdqu "); | 2001 AppendToBuffer("movdqu "); |
1898 data += 3; | 2002 data += 3; |
1899 int mod, regop, rm; | 2003 int mod, regop, rm; |
1900 get_modrm(*data, &mod, ®op, &rm); | 2004 get_modrm(*data, &mod, ®op, &rm); |
1901 data += PrintRightXMMOperand(data); | 2005 data += PrintRightXMMOperand(data); |
1902 AppendToBuffer(",%s", NameOfXMMRegister(regop)); | 2006 AppendToBuffer(",%s", NameOfXMMRegister(regop)); |
| 2007 } else if (b2 == 0xB8) { |
| 2008 data += 3; |
| 2009 int mod, regop, rm; |
| 2010 get_modrm(*data, &mod, ®op, &rm); |
| 2011 AppendToBuffer("popcnt %s,", NameOfCPURegister(regop)); |
| 2012 data += PrintRightOperand(data); |
| 2013 } else if (b2 == 0xBC) { |
| 2014 data += 3; |
| 2015 int mod, regop, rm; |
| 2016 get_modrm(*data, &mod, ®op, &rm); |
| 2017 AppendToBuffer("tzcnt %s,", NameOfCPURegister(regop)); |
| 2018 data += PrintRightOperand(data); |
| 2019 } else if (b2 == 0xBD) { |
| 2020 data += 3; |
| 2021 int mod, regop, rm; |
| 2022 get_modrm(*data, &mod, ®op, &rm); |
| 2023 AppendToBuffer("lzcnt %s,", NameOfCPURegister(regop)); |
| 2024 data += PrintRightOperand(data); |
1903 } else { | 2025 } else { |
1904 const char* mnem = "?"; | 2026 const char* mnem = "?"; |
1905 switch (b2) { | 2027 switch (b2) { |
1906 case 0x2A: | 2028 case 0x2A: |
1907 mnem = "cvtsi2ss"; | 2029 mnem = "cvtsi2ss"; |
1908 break; | 2030 break; |
1909 case 0x2C: | 2031 case 0x2C: |
1910 mnem = "cvttss2si"; | 2032 mnem = "cvttss2si"; |
1911 break; | 2033 break; |
1912 case 0x2D: | 2034 case 0x2D: |
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2096 fprintf(f, " "); | 2218 fprintf(f, " "); |
2097 } | 2219 } |
2098 fprintf(f, " %s\n", buffer.start()); | 2220 fprintf(f, " %s\n", buffer.start()); |
2099 } | 2221 } |
2100 } | 2222 } |
2101 | 2223 |
2102 | 2224 |
2103 } // namespace disasm | 2225 } // namespace disasm |
2104 | 2226 |
2105 #endif // V8_TARGET_ARCH_IA32 | 2227 #endif // V8_TARGET_ARCH_IA32 |
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