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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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1307 vss(0x5f, dst, src1, src2); | 1307 vss(0x5f, dst, src1, src2); |
1308 } | 1308 } |
1309 void vminss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { | 1309 void vminss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { |
1310 vminss(dst, src1, Operand(src2)); | 1310 vminss(dst, src1, Operand(src2)); |
1311 } | 1311 } |
1312 void vminss(XMMRegister dst, XMMRegister src1, const Operand& src2) { | 1312 void vminss(XMMRegister dst, XMMRegister src1, const Operand& src2) { |
1313 vss(0x5d, dst, src1, src2); | 1313 vss(0x5d, dst, src1, src2); |
1314 } | 1314 } |
1315 void vss(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2); | 1315 void vss(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2); |
1316 | 1316 |
| 1317 // BMI instruction |
| 1318 void andn(Register dst, Register src1, Register src2) { |
| 1319 andn(dst, src1, Operand(src2)); |
| 1320 } |
| 1321 void andn(Register dst, Register src1, const Operand& src2) { |
| 1322 bmi1(0xf2, dst, src1, src2); |
| 1323 } |
| 1324 void bextr(Register dst, Register src1, Register src2) { |
| 1325 bextr(dst, Operand(src1), src2); |
| 1326 } |
| 1327 void bextr(Register dst, const Operand& src1, Register src2) { |
| 1328 bmi1(0xf7, dst, src2, src1); |
| 1329 } |
| 1330 void blsi(Register dst, Register src) { blsi(dst, Operand(src)); } |
| 1331 void blsi(Register dst, const Operand& src) { |
| 1332 Register ireg = {3}; |
| 1333 bmi1(0xf3, ireg, dst, src); |
| 1334 } |
| 1335 void blsmsk(Register dst, Register src) { blsmsk(dst, Operand(src)); } |
| 1336 void blsmsk(Register dst, const Operand& src) { |
| 1337 Register ireg = {2}; |
| 1338 bmi1(0xf3, ireg, dst, src); |
| 1339 } |
| 1340 void blsr(Register dst, Register src) { blsr(dst, Operand(src)); } |
| 1341 void blsr(Register dst, const Operand& src) { |
| 1342 Register ireg = {1}; |
| 1343 bmi1(0xf3, ireg, dst, src); |
| 1344 } |
| 1345 void tzcnt(Register dst, Register src) { tzcnt(dst, Operand(src)); } |
| 1346 void tzcnt(Register dst, const Operand& src); |
| 1347 |
| 1348 void lzcnt(Register dst, Register src) { lzcnt(dst, Operand(src)); } |
| 1349 void lzcnt(Register dst, const Operand& src); |
| 1350 |
| 1351 void popcnt(Register dst, Register src) { popcnt(dst, Operand(src)); } |
| 1352 void popcnt(Register dst, const Operand& src); |
| 1353 |
| 1354 void bzhi(Register dst, Register src1, Register src2) { |
| 1355 bzhi(dst, Operand(src1), src2); |
| 1356 } |
| 1357 void bzhi(Register dst, const Operand& src1, Register src2) { |
| 1358 bmi2(kNone, 0xf5, dst, src2, src1); |
| 1359 } |
| 1360 void mulx(Register dst1, Register dst2, Register src) { |
| 1361 mulx(dst1, dst2, Operand(src)); |
| 1362 } |
| 1363 void mulx(Register dst1, Register dst2, const Operand& src) { |
| 1364 bmi2(kF2, 0xf6, dst1, dst2, src); |
| 1365 } |
| 1366 void pdep(Register dst, Register src1, Register src2) { |
| 1367 pdep(dst, src1, Operand(src2)); |
| 1368 } |
| 1369 void pdep(Register dst, Register src1, const Operand& src2) { |
| 1370 bmi2(kF2, 0xf5, dst, src1, src2); |
| 1371 } |
| 1372 void pext(Register dst, Register src1, Register src2) { |
| 1373 pext(dst, src1, Operand(src2)); |
| 1374 } |
| 1375 void pext(Register dst, Register src1, const Operand& src2) { |
| 1376 bmi2(kF3, 0xf5, dst, src1, src2); |
| 1377 } |
| 1378 void sarx(Register dst, Register src1, Register src2) { |
| 1379 sarx(dst, Operand(src1), src2); |
| 1380 } |
| 1381 void sarx(Register dst, const Operand& src1, Register src2) { |
| 1382 bmi2(kF3, 0xf7, dst, src2, src1); |
| 1383 } |
| 1384 void shlx(Register dst, Register src1, Register src2) { |
| 1385 shlx(dst, Operand(src1), src2); |
| 1386 } |
| 1387 void shlx(Register dst, const Operand& src1, Register src2) { |
| 1388 bmi2(k66, 0xf7, dst, src2, src1); |
| 1389 } |
| 1390 void shrx(Register dst, Register src1, Register src2) { |
| 1391 shrx(dst, Operand(src1), src2); |
| 1392 } |
| 1393 void shrx(Register dst, const Operand& src1, Register src2) { |
| 1394 bmi2(kF2, 0xf7, dst, src2, src1); |
| 1395 } |
| 1396 void rorx(Register dst, Register src, byte imm8) { |
| 1397 rorx(dst, Operand(src), imm8); |
| 1398 } |
| 1399 void rorx(Register dst, const Operand& src, byte imm8); |
| 1400 |
1317 // Prefetch src position into cache level. | 1401 // Prefetch src position into cache level. |
1318 // Level 1, 2 or 3 specifies CPU cache level. Level 0 specifies a | 1402 // Level 1, 2 or 3 specifies CPU cache level. Level 0 specifies a |
1319 // non-temporal | 1403 // non-temporal |
1320 void prefetch(const Operand& src, int level); | 1404 void prefetch(const Operand& src, int level); |
1321 // TODO(lrn): Need SFENCE for movnt? | 1405 // TODO(lrn): Need SFENCE for movnt? |
1322 | 1406 |
1323 // Check the code size generated from label to here. | 1407 // Check the code size generated from label to here. |
1324 int SizeOfCodeGeneratedSince(Label* label) { | 1408 int SizeOfCodeGeneratedSince(Label* label) { |
1325 return pc_offset() - label->pos(); | 1409 return pc_offset() - label->pos(); |
1326 } | 1410 } |
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1418 void emit_arith(int sel, Operand dst, const Immediate& x); | 1502 void emit_arith(int sel, Operand dst, const Immediate& x); |
1419 | 1503 |
1420 void emit_operand(Register reg, const Operand& adr); | 1504 void emit_operand(Register reg, const Operand& adr); |
1421 | 1505 |
1422 void emit_label(Label* label); | 1506 void emit_label(Label* label); |
1423 | 1507 |
1424 void emit_farith(int b1, int b2, int i); | 1508 void emit_farith(int b1, int b2, int i); |
1425 | 1509 |
1426 // Emit vex prefix | 1510 // Emit vex prefix |
1427 enum SIMDPrefix { kNone = 0x0, k66 = 0x1, kF3 = 0x2, kF2 = 0x3 }; | 1511 enum SIMDPrefix { kNone = 0x0, k66 = 0x1, kF3 = 0x2, kF2 = 0x3 }; |
1428 enum VectorLength { kL128 = 0x0, kL256 = 0x4, kLIG = kL128 }; | 1512 enum VectorLength { kL128 = 0x0, kL256 = 0x4, kLIG = kL128, kLZ = kL128 }; |
1429 enum VexW { kW0 = 0x0, kW1 = 0x80, kWIG = kW0 }; | 1513 enum VexW { kW0 = 0x0, kW1 = 0x80, kWIG = kW0 }; |
1430 enum LeadingOpcode { k0F = 0x1, k0F38 = 0x2, k0F3A = 0x2 }; | 1514 enum LeadingOpcode { k0F = 0x1, k0F38 = 0x2, k0F3A = 0x3 }; |
1431 inline void emit_vex_prefix(XMMRegister v, VectorLength l, SIMDPrefix pp, | 1515 inline void emit_vex_prefix(XMMRegister v, VectorLength l, SIMDPrefix pp, |
1432 LeadingOpcode m, VexW w); | 1516 LeadingOpcode m, VexW w); |
| 1517 inline void emit_vex_prefix(Register v, VectorLength l, SIMDPrefix pp, |
| 1518 LeadingOpcode m, VexW w); |
1433 | 1519 |
1434 // labels | 1520 // labels |
1435 void print(Label* L); | 1521 void print(Label* L); |
1436 void bind_to(Label* L, int pos); | 1522 void bind_to(Label* L, int pos); |
1437 | 1523 |
1438 // displacements | 1524 // displacements |
1439 inline Displacement disp_at(Label* L); | 1525 inline Displacement disp_at(Label* L); |
1440 inline void disp_at_put(Label* L, Displacement disp); | 1526 inline void disp_at_put(Label* L, Displacement disp); |
1441 inline void emit_disp(Label* L, Displacement::Type type); | 1527 inline void emit_disp(Label* L, Displacement::Type type); |
1442 inline void emit_near_disp(Label* L); | 1528 inline void emit_near_disp(Label* L); |
1443 | 1529 |
| 1530 // Most BMI instructions are similiar. |
| 1531 void bmi1(byte op, Register reg, Register vreg, const Operand& rm); |
| 1532 void bmi2(SIMDPrefix pp, byte op, Register reg, Register vreg, |
| 1533 const Operand& rm); |
| 1534 |
1444 // record reloc info for current pc_ | 1535 // record reloc info for current pc_ |
1445 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); | 1536 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); |
1446 | 1537 |
1447 friend class CodePatcher; | 1538 friend class CodePatcher; |
1448 friend class EnsureSpace; | 1539 friend class EnsureSpace; |
1449 | 1540 |
1450 // Internal reference positions, required for (potential) patching in | 1541 // Internal reference positions, required for (potential) patching in |
1451 // GrowBuffer(); contains only those internal references whose labels | 1542 // GrowBuffer(); contains only those internal references whose labels |
1452 // are already bound. | 1543 // are already bound. |
1453 std::deque<int> internal_reference_positions_; | 1544 std::deque<int> internal_reference_positions_; |
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1483 private: | 1574 private: |
1484 Assembler* assembler_; | 1575 Assembler* assembler_; |
1485 #ifdef DEBUG | 1576 #ifdef DEBUG |
1486 int space_before_; | 1577 int space_before_; |
1487 #endif | 1578 #endif |
1488 }; | 1579 }; |
1489 | 1580 |
1490 } } // namespace v8::internal | 1581 } } // namespace v8::internal |
1491 | 1582 |
1492 #endif // V8_IA32_ASSEMBLER_IA32_H_ | 1583 #endif // V8_IA32_ASSEMBLER_IA32_H_ |
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