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Side by Side Diff: src/compiler/arm64/instruction-codes-arm64.h

Issue 1066393002: [turbofan] Add new Float32Abs and Float64Abs operators. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Fix comment. Created 5 years, 8 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 67 matching lines...) Expand 10 before | Expand all | Expand 10 after
78 V(Arm64Claim) \ 78 V(Arm64Claim) \
79 V(Arm64Poke) \ 79 V(Arm64Poke) \
80 V(Arm64PokePair) \ 80 V(Arm64PokePair) \
81 V(Arm64Float32Cmp) \ 81 V(Arm64Float32Cmp) \
82 V(Arm64Float32Add) \ 82 V(Arm64Float32Add) \
83 V(Arm64Float32Sub) \ 83 V(Arm64Float32Sub) \
84 V(Arm64Float32Mul) \ 84 V(Arm64Float32Mul) \
85 V(Arm64Float32Div) \ 85 V(Arm64Float32Div) \
86 V(Arm64Float32Max) \ 86 V(Arm64Float32Max) \
87 V(Arm64Float32Min) \ 87 V(Arm64Float32Min) \
88 V(Arm64Float32Abs) \
88 V(Arm64Float32Sqrt) \ 89 V(Arm64Float32Sqrt) \
89 V(Arm64Float64Cmp) \ 90 V(Arm64Float64Cmp) \
90 V(Arm64Float64Add) \ 91 V(Arm64Float64Add) \
91 V(Arm64Float64Sub) \ 92 V(Arm64Float64Sub) \
92 V(Arm64Float64Mul) \ 93 V(Arm64Float64Mul) \
93 V(Arm64Float64Div) \ 94 V(Arm64Float64Div) \
94 V(Arm64Float64Mod) \ 95 V(Arm64Float64Mod) \
95 V(Arm64Float64Max) \ 96 V(Arm64Float64Max) \
96 V(Arm64Float64Min) \ 97 V(Arm64Float64Min) \
98 V(Arm64Float64Abs) \
97 V(Arm64Float64Neg) \ 99 V(Arm64Float64Neg) \
98 V(Arm64Float64Sqrt) \ 100 V(Arm64Float64Sqrt) \
99 V(Arm64Float64RoundDown) \ 101 V(Arm64Float64RoundDown) \
100 V(Arm64Float64RoundTiesAway) \ 102 V(Arm64Float64RoundTiesAway) \
101 V(Arm64Float64RoundTruncate) \ 103 V(Arm64Float64RoundTruncate) \
102 V(Arm64Float64RoundUp) \ 104 V(Arm64Float64RoundUp) \
103 V(Arm64Float32ToFloat64) \ 105 V(Arm64Float32ToFloat64) \
104 V(Arm64Float64ToFloat32) \ 106 V(Arm64Float64ToFloat32) \
105 V(Arm64Float64ToInt32) \ 107 V(Arm64Float64ToInt32) \
106 V(Arm64Float64ToUint32) \ 108 V(Arm64Float64ToUint32) \
(...skipping 44 matching lines...) Expand 10 before | Expand all | Expand 10 after
151 V(Operand2_R_UXTB) /* %r0 UXTB (unsigned extend byte) */ \ 153 V(Operand2_R_UXTB) /* %r0 UXTB (unsigned extend byte) */ \
152 V(Operand2_R_UXTH) /* %r0 UXTH (unsigned extend halfword) */ \ 154 V(Operand2_R_UXTH) /* %r0 UXTH (unsigned extend halfword) */ \
153 V(Operand2_R_SXTB) /* %r0 SXTB (signed extend byte) */ \ 155 V(Operand2_R_SXTB) /* %r0 SXTB (signed extend byte) */ \
154 V(Operand2_R_SXTH) /* %r0 SXTH (signed extend halfword) */ 156 V(Operand2_R_SXTH) /* %r0 SXTH (signed extend halfword) */
155 157
156 } // namespace internal 158 } // namespace internal
157 } // namespace compiler 159 } // namespace compiler
158 } // namespace v8 160 } // namespace v8
159 161
160 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 162 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
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