[turbofan] Add new Float32Abs and Float64Abs operators.

src/compiler/arm/instruction-codes-arm.h

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
 
 namespace v8 {
 namespace internal {
 namespace compiler {
@@ skipping 33 matching lines @@
   V(ArmUxth)                       \
   V(ArmUxtab)                      \
   V(ArmUxtah)                      \
   V(ArmVcmpF32)                    \
   V(ArmVaddF32)                    \
   V(ArmVsubF32)                    \
   V(ArmVmulF32)                    \
   V(ArmVmlaF32)                    \
   V(ArmVmlsF32)                    \
   V(ArmVdivF32)                    \
+  V(ArmVabsF32)                    \
   V(ArmVnegF32)                    \
   V(ArmVsqrtF32)                   \
   V(ArmVcmpF64)                    \
   V(ArmVaddF64)                    \
   V(ArmVsubF64)                    \
   V(ArmVmulF64)                    \
   V(ArmVmlaF64)                    \
   V(ArmVmlsF64)                    \
   V(ArmVdivF64)                    \
   V(ArmVmodF64)                    \
+  V(ArmVabsF64)                    \
   V(ArmVnegF64)                    \
   V(ArmVsqrtF64)                   \
   V(ArmVrintmF64)                  \
   V(ArmVrintpF64)                  \
   V(ArmVrintzF64)                  \
   V(ArmVrintaF64)                  \
   V(ArmVcvtF32F64)                 \
   V(ArmVcvtF64F32)                 \
   V(ArmVcvtF64S32)                 \
   V(ArmVcvtF64U32)                 \
@@ skipping 36 matching lines @@
   V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
   V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
   V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
   V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_