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Issue 1064813003: ARM64: Support sign extend for add and subtract (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 8 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/compiler/code-generator.h" 5 #include "src/compiler/code-generator.h"
6 6
7 #include "src/arm64/macro-assembler-arm64.h" 7 #include "src/arm64/macro-assembler-arm64.h"
8 #include "src/compiler/code-generator-impl.h" 8 #include "src/compiler/code-generator-impl.h"
9 #include "src/compiler/gap-resolver.h" 9 #include "src/compiler/gap-resolver.h"
10 #include "src/compiler/node-matchers.h" 10 #include "src/compiler/node-matchers.h"
(...skipping 57 matching lines...) Expand 10 before | Expand all | Expand 10 after
68 case kMode_Operand2_R_LSR_I: 68 case kMode_Operand2_R_LSR_I:
69 return Operand(InputRegister32(index), LSR, InputInt5(index + 1)); 69 return Operand(InputRegister32(index), LSR, InputInt5(index + 1));
70 case kMode_Operand2_R_ASR_I: 70 case kMode_Operand2_R_ASR_I:
71 return Operand(InputRegister32(index), ASR, InputInt5(index + 1)); 71 return Operand(InputRegister32(index), ASR, InputInt5(index + 1));
72 case kMode_Operand2_R_ROR_I: 72 case kMode_Operand2_R_ROR_I:
73 return Operand(InputRegister32(index), ROR, InputInt5(index + 1)); 73 return Operand(InputRegister32(index), ROR, InputInt5(index + 1));
74 case kMode_Operand2_R_UXTB: 74 case kMode_Operand2_R_UXTB:
75 return Operand(InputRegister32(index), UXTB); 75 return Operand(InputRegister32(index), UXTB);
76 case kMode_Operand2_R_UXTH: 76 case kMode_Operand2_R_UXTH:
77 return Operand(InputRegister32(index), UXTH); 77 return Operand(InputRegister32(index), UXTH);
78 case kMode_Operand2_R_SXTB:
79 return Operand(InputRegister32(index), SXTB);
80 case kMode_Operand2_R_SXTH:
81 return Operand(InputRegister32(index), SXTH);
78 case kMode_MRI: 82 case kMode_MRI:
79 case kMode_MRR: 83 case kMode_MRR:
80 break; 84 break;
81 } 85 }
82 UNREACHABLE(); 86 UNREACHABLE();
83 return Operand(-1); 87 return Operand(-1);
84 } 88 }
85 89
86 Operand InputOperand2_64(size_t index) { 90 Operand InputOperand2_64(size_t index) {
87 switch (AddressingModeField::decode(instr_->opcode())) { 91 switch (AddressingModeField::decode(instr_->opcode())) {
88 case kMode_None: 92 case kMode_None:
89 return InputOperand64(index); 93 return InputOperand64(index);
90 case kMode_Operand2_R_LSL_I: 94 case kMode_Operand2_R_LSL_I:
91 return Operand(InputRegister64(index), LSL, InputInt6(index + 1)); 95 return Operand(InputRegister64(index), LSL, InputInt6(index + 1));
92 case kMode_Operand2_R_LSR_I: 96 case kMode_Operand2_R_LSR_I:
93 return Operand(InputRegister64(index), LSR, InputInt6(index + 1)); 97 return Operand(InputRegister64(index), LSR, InputInt6(index + 1));
94 case kMode_Operand2_R_ASR_I: 98 case kMode_Operand2_R_ASR_I:
95 return Operand(InputRegister64(index), ASR, InputInt6(index + 1)); 99 return Operand(InputRegister64(index), ASR, InputInt6(index + 1));
96 case kMode_Operand2_R_ROR_I: 100 case kMode_Operand2_R_ROR_I:
97 return Operand(InputRegister64(index), ROR, InputInt6(index + 1)); 101 return Operand(InputRegister64(index), ROR, InputInt6(index + 1));
98 case kMode_Operand2_R_UXTB: 102 case kMode_Operand2_R_UXTB:
99 return Operand(InputRegister64(index), UXTB); 103 return Operand(InputRegister64(index), UXTB);
100 case kMode_Operand2_R_UXTH: 104 case kMode_Operand2_R_UXTH:
101 return Operand(InputRegister64(index), UXTH); 105 return Operand(InputRegister64(index), UXTH);
106 case kMode_Operand2_R_SXTB:
107 return Operand(InputRegister64(index), SXTB);
108 case kMode_Operand2_R_SXTH:
109 return Operand(InputRegister64(index), SXTH);
102 case kMode_MRI: 110 case kMode_MRI:
103 case kMode_MRR: 111 case kMode_MRR:
104 break; 112 break;
105 } 113 }
106 UNREACHABLE(); 114 UNREACHABLE();
107 return Operand(-1); 115 return Operand(-1);
108 } 116 }
109 117
110 MemOperand MemoryOperand(size_t* first_index) { 118 MemOperand MemoryOperand(size_t* first_index) {
111 const size_t index = *first_index; 119 const size_t index = *first_index;
112 switch (AddressingModeField::decode(instr_->opcode())) { 120 switch (AddressingModeField::decode(instr_->opcode())) {
113 case kMode_None: 121 case kMode_None:
114 case kMode_Operand2_R_LSL_I: 122 case kMode_Operand2_R_LSL_I:
115 case kMode_Operand2_R_LSR_I: 123 case kMode_Operand2_R_LSR_I:
116 case kMode_Operand2_R_ASR_I: 124 case kMode_Operand2_R_ASR_I:
117 case kMode_Operand2_R_ROR_I: 125 case kMode_Operand2_R_ROR_I:
118 case kMode_Operand2_R_UXTB: 126 case kMode_Operand2_R_UXTB:
119 case kMode_Operand2_R_UXTH: 127 case kMode_Operand2_R_UXTH:
128 case kMode_Operand2_R_SXTB:
129 case kMode_Operand2_R_SXTH:
120 break; 130 break;
121 case kMode_MRI: 131 case kMode_MRI:
122 *first_index += 2; 132 *first_index += 2;
123 return MemOperand(InputRegister(index + 0), InputInt32(index + 1)); 133 return MemOperand(InputRegister(index + 0), InputInt32(index + 1));
124 case kMode_MRR: 134 case kMode_MRR:
125 *first_index += 2; 135 *first_index += 2;
126 return MemOperand(InputRegister(index + 0), InputRegister(index + 1)); 136 return MemOperand(InputRegister(index + 0), InputRegister(index + 1));
127 } 137 }
128 UNREACHABLE(); 138 UNREACHABLE();
129 return MemOperand(no_reg); 139 return MemOperand(no_reg);
(...skipping 1121 matching lines...) Expand 10 before | Expand all | Expand 10 after
1251 } 1261 }
1252 } 1262 }
1253 MarkLazyDeoptSite(); 1263 MarkLazyDeoptSite();
1254 } 1264 }
1255 1265
1256 #undef __ 1266 #undef __
1257 1267
1258 } // namespace compiler 1268 } // namespace compiler
1259 } // namespace internal 1269 } // namespace internal
1260 } // namespace v8 1270 } // namespace v8
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