Fixes ARM multiplication instruction version checking.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 392 matching lines @@
 
 // Like mul, but sets condition flags.
 void Assembler::muls(Register rd, Register rn, Register rm, Condition cond) {
   EmitMulOp(cond, B20, R0, rd, rn, rm);
 }
 
 
 void Assembler::mla(Register rd, Register rn,
                     Register rm, Register ra, Condition cond) {
   // rd <- ra + rn * rm.
-  if (TargetCPUFeatures::arm_version() == ARMv7) {
-    // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
-    EmitMulOp(cond, B21, ra, rd, rn, rm);
-  } else {
-    mul(IP, rn, rm, cond);
-    add(rd, ra, Operand(IP), cond);
-  }
+  // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
+  EmitMulOp(cond, B21, ra, rd, rn, rm);
 }
 
 
 void Assembler::mls(Register rd, Register rn,
                     Register rm, Register ra, Condition cond) {
   // rd <- ra - rn * rm.
   if (TargetCPUFeatures::arm_version() == ARMv7) {
     // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
     EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
   } else {
     mul(IP, rn, rm, cond);
     sub(rd, ra, Operand(IP), cond);
   }
 }
 
 
 void Assembler::smull(Register rd_lo, Register rd_hi,
                       Register rn, Register rm, Condition cond) {
   // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
   EmitMulOp(cond, B23 | B22, rd_lo, rd_hi, rn, rm);
 }
 
 
 void Assembler::umull(Register rd_lo, Register rd_hi,
                       Register rn, Register rm, Condition cond) {
-  ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
   // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
   EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm);
 }
 
 
-void Assembler::smlal(Register rd_lo, Register rd_hi,
-                      Register rn, Register rm, Condition cond) {
-  ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
-  // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
-  EmitMulOp(cond, B23 | B22 | B21, rd_lo, rd_hi, rn, rm);
-}
-
-
 void Assembler::umlal(Register rd_lo, Register rd_hi,
                       Register rn, Register rm, Condition cond) {
-  ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
   // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
   EmitMulOp(cond, B23 | B21, rd_lo, rd_hi, rn, rm);
 }
 
 
 void Assembler::umaal(Register rd_lo, Register rd_hi,
-                      Register rn, Register rm, Condition cond) {
-  ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
-  // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
-  EmitMulOp(cond, B22, rd_lo, rd_hi, rn, rm);
+                      Register rn, Register rm) {
+  ASSERT(rd_lo != IP);
+  ASSERT(rd_hi != IP);
+  ASSERT(rn != IP);
+  ASSERT(rm != IP);
+  if (TargetCPUFeatures::arm_version() != ARMv5TE) {
+    // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
+    EmitMulOp(AL, B22, rd_lo, rd_hi, rn, rm);
+  } else {
+    mov(IP, Operand(0));
+    umlal(rd_lo, IP, rn, rm);
+    adds(rd_lo, rd_lo, Operand(rd_hi));
+    adc(rd_hi, IP, Operand(0));
+  }
 }
 
 
 void Assembler::EmitDivOp(Condition cond, int32_t opcode,
                           Register rd, Register rn, Register rm) {
   ASSERT(TargetCPUFeatures::integer_division_supported());
   ASSERT(rd != kNoRegister);
   ASSERT(rn != kNoRegister);
   ASSERT(rm != kNoRegister);
   ASSERT(cond != kNoCondition);
@@ skipping 3099 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM