| Index: src/compiler/pipeline.cc
|
| diff --git a/src/compiler/pipeline.cc b/src/compiler/pipeline.cc
|
| index ef1c83fcb81d3fcd5f7a587990ce315d009a3ce4..c015fba412ea79e7b1f2879d4e11fe959b54f3b8 100644
|
| --- a/src/compiler/pipeline.cc
|
| +++ b/src/compiler/pipeline.cc
|
| @@ -742,23 +742,23 @@ struct BuildLiveRangesPhase {
|
| };
|
|
|
|
|
| +template <typename RegAllocator>
|
| struct AllocateGeneralRegistersPhase {
|
| static const char* phase_name() { return "allocate general registers"; }
|
|
|
| void Run(PipelineData* data, Zone* temp_zone) {
|
| - LinearScanAllocator allocator(data->register_allocation_data(),
|
| - GENERAL_REGISTERS);
|
| + RegAllocator allocator(data->register_allocation_data(), GENERAL_REGISTERS);
|
| allocator.AllocateRegisters();
|
| }
|
| };
|
|
|
|
|
| +template <typename RegAllocator>
|
| struct AllocateDoubleRegistersPhase {
|
| static const char* phase_name() { return "allocate double registers"; }
|
|
|
| void Run(PipelineData* data, Zone* temp_zone) {
|
| - LinearScanAllocator allocator(data->register_allocation_data(),
|
| - DOUBLE_REGISTERS);
|
| + RegAllocator allocator(data->register_allocation_data(), DOUBLE_REGISTERS);
|
| allocator.AllocateRegisters();
|
| }
|
| };
|
| @@ -1269,8 +1269,13 @@ void Pipeline::AllocateRegisters(const RegisterConfiguration* config,
|
| if (verifier != nullptr) {
|
| CHECK(!data->register_allocation_data()->ExistsUseWithoutDefinition());
|
| }
|
| - Run<AllocateGeneralRegistersPhase>();
|
| - Run<AllocateDoubleRegistersPhase>();
|
| + if (FLAG_turbo_greedy_regalloc) {
|
| + Run<AllocateGeneralRegistersPhase<GreedyAllocator>>();
|
| + Run<AllocateDoubleRegistersPhase<GreedyAllocator>>();
|
| + } else {
|
| + Run<AllocateGeneralRegistersPhase<LinearScanAllocator>>();
|
| + Run<AllocateDoubleRegistersPhase<LinearScanAllocator>>();
|
| + }
|
| Run<AssignSpillSlotsPhase>();
|
|
|
| Run<CommitAssignmentPhase>();
|
|
|