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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 | 5 |
6 // Declares a Simulator for MIPS instructions if we are not generating a native | 6 // Declares a Simulator for MIPS instructions if we are not generating a native |
7 // MIPS binary. This Simulator allows us to run and debug MIPS code generation | 7 // MIPS binary. This Simulator allows us to run and debug MIPS code generation |
8 // on regular desktop machines. | 8 // on regular desktop machines. |
9 // V8 calls into generated code by "calling" the CALL_GENERATED_CODE macro, | 9 // V8 calls into generated code by "calling" the CALL_GENERATED_CODE macro, |
10 // which will start execution in the Simulator or forwards to the real entry | 10 // which will start execution in the Simulator or forwards to the real entry |
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306 | 306 |
307 // Operations depending on endianness. | 307 // Operations depending on endianness. |
308 // Get Double Higher / Lower word. | 308 // Get Double Higher / Lower word. |
309 inline int32_t GetDoubleHIW(double* addr); | 309 inline int32_t GetDoubleHIW(double* addr); |
310 inline int32_t GetDoubleLOW(double* addr); | 310 inline int32_t GetDoubleLOW(double* addr); |
311 // Set Double Higher / Lower word. | 311 // Set Double Higher / Lower word. |
312 inline int32_t SetDoubleHIW(double* addr); | 312 inline int32_t SetDoubleHIW(double* addr); |
313 inline int32_t SetDoubleLOW(double* addr); | 313 inline int32_t SetDoubleLOW(double* addr); |
314 | 314 |
315 // functions called from DecodeTypeRegister | 315 // functions called from DecodeTypeRegister |
316 void DecodeTypeRegisterCOP1(Instruction* instr, const int64_t& rs_reg, | 316 void DecodeTypeRegisterCOP1(Instruction* instr, const int32_t& rs_reg, |
317 const int64_t& rs, const uint64_t& rs_u, | 317 const int64_t& rs, const uint64_t& rs_u, |
318 const int64_t& rt_reg, const int64_t& rt, | 318 const int32_t& rt_reg, const int64_t& rt, |
319 const uint64_t& rt_u, const int64_t& rd_reg, | 319 const uint64_t& rt_u, const int32_t& rd_reg, |
320 const int32_t& fr_reg, const int32_t& fs_reg, | 320 const int32_t& fr_reg, const int32_t& fs_reg, |
321 const int32_t& ft_reg, const int64_t& fd_reg, | 321 const int32_t& ft_reg, const int32_t& fd_reg, |
322 int64_t& alu_out); | 322 int64_t& alu_out); |
323 | 323 |
324 void DecodeTypeRegisterCOP1X(Instruction* instr, const int32_t& fr_reg, | 324 void DecodeTypeRegisterCOP1X(Instruction* instr, const int32_t& fr_reg, |
325 const int32_t& fs_reg, const int32_t& ft_reg, | 325 const int32_t& fs_reg, const int32_t& ft_reg, |
326 const int64_t& fd_reg); | 326 const int32_t& fd_reg); |
327 | 327 |
328 void DecodeTypeRegisterSPECIAL( | 328 void DecodeTypeRegisterSPECIAL( |
329 Instruction* instr, const int64_t& rs_reg, const int64_t& rs, | 329 Instruction* instr, const int64_t& rs_reg, const int64_t& rs, |
330 const uint64_t& rs_u, const int64_t& rt_reg, const int64_t& rt, | 330 const uint64_t& rs_u, const int64_t& rt_reg, const int64_t& rt, |
331 const uint64_t& rt_u, const int64_t& rd_reg, const int32_t& fr_reg, | 331 const uint64_t& rt_u, const int64_t& rd_reg, const int32_t& fr_reg, |
332 const int32_t& fs_reg, const int32_t& ft_reg, const int64_t& fd_reg, | 332 const int32_t& fs_reg, const int32_t& ft_reg, const int64_t& fd_reg, |
333 int64_t& i64hilo, uint64_t& u64hilo, int64_t& alu_out, bool& do_interrupt, | 333 int64_t& i64hilo, uint64_t& u64hilo, int64_t& alu_out, bool& do_interrupt, |
334 int64_t& current_pc, int64_t& next_pc, int64_t& return_addr_reg, | 334 int64_t& current_pc, int64_t& next_pc, int64_t& return_addr_reg, |
335 int64_t& i128resultH, int64_t& i128resultL); | 335 int64_t& i128resultH, int64_t& i128resultL); |
336 | 336 |
337 void DecodeTypeRegisterSPECIAL2(Instruction* instr, const int64_t& rd_reg, | 337 void DecodeTypeRegisterSPECIAL2(Instruction* instr, const int64_t& rd_reg, |
338 int64_t& alu_out); | 338 int64_t& alu_out); |
339 | 339 |
340 void DecodeTypeRegisterSPECIAL3(Instruction* instr, const int64_t& rt_reg, | 340 void DecodeTypeRegisterSPECIAL3(Instruction* instr, const int64_t& rt_reg, |
341 int64_t& alu_out); | 341 int64_t& alu_out); |
342 | 342 |
343 void DecodeTypeRegisterSRsType(Instruction* instr, const int32_t& fs_reg, | 343 void DecodeTypeRegisterSRsType(Instruction* instr, const int32_t& fs_reg, |
344 const int32_t& ft_reg, const int64_t& fd_reg); | 344 const int32_t& ft_reg, const int32_t& fd_reg); |
345 | 345 |
346 void DecodeTypeRegisterDRsType(Instruction* instr, const int32_t& fs_reg, | 346 void DecodeTypeRegisterDRsType(Instruction* instr, const int32_t& fs_reg, |
347 const int64_t& ft_reg, const int32_t& fd_reg); | 347 const int32_t& ft_reg, const int32_t& fd_reg); |
348 | 348 |
349 void DecodeTypeRegisterWRsType(Instruction* instr, const int32_t& fs_reg, | 349 void DecodeTypeRegisterWRsType(Instruction* instr, const int32_t& fs_reg, |
350 const int32_t& fd_reg, int64_t& alu_out); | 350 const int32_t& fd_reg, int64_t& alu_out); |
351 | 351 |
352 void DecodeTypeRegisterLRsType(Instruction* instr, const int32_t& fs_reg, | 352 void DecodeTypeRegisterLRsType(Instruction* instr, const int32_t& fs_reg, |
353 const int32_t& fd_reg, const int32_t& ft_reg); | 353 const int32_t& fd_reg, const int32_t& ft_reg); |
354 // Executing is handled based on the instruction type. | 354 // Executing is handled based on the instruction type. |
355 void DecodeTypeRegister(Instruction* instr); | 355 void DecodeTypeRegister(Instruction* instr); |
356 | 356 |
357 // Helper function for DecodeTypeRegister. | 357 // Helper function for DecodeTypeRegister. |
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512 | 512 |
513 static inline void UnregisterCTryCatch() { | 513 static inline void UnregisterCTryCatch() { |
514 Simulator::current(Isolate::Current())->PopAddress(); | 514 Simulator::current(Isolate::Current())->PopAddress(); |
515 } | 515 } |
516 }; | 516 }; |
517 | 517 |
518 } } // namespace v8::internal | 518 } } // namespace v8::internal |
519 | 519 |
520 #endif // !defined(USE_SIMULATOR) | 520 #endif // !defined(USE_SIMULATOR) |
521 #endif // V8_MIPS_SIMULATOR_MIPS_H_ | 521 #endif // V8_MIPS_SIMULATOR_MIPS_H_ |
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