MIPS: Major fixes and clean-up in asm. for instruction encoding.

src/mips64/simulator-mips64.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>
 #include <stdarg.h>
 #include <stdlib.h>
 #include <cmath>
 
 #include "src/v8.h"
@@ skipping 2255 matching lines @@
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterSRsType(Instruction* instr,
                                           const int32_t& fs_reg,
                                           const int32_t& ft_reg,
-                                          const int64_t& fd_reg) {
+                                          const int32_t& fd_reg) {
   float fs, ft;
   fs = get_fpu_register_float(fs_reg);
   ft = get_fpu_register_float(ft_reg);
   uint32_t cc, fcsr_cc;
   cc = instr->FCccValue();
   fcsr_cc = get_fcsr_condition_bit(cc);
   switch (instr->FunctionFieldRaw()) {
     case ADD_D:
       set_fpu_register_float(fd_reg, fs + ft);
       break;
@@ skipping 45 matching lines @@
     default:
       // CVT_W_S CVT_L_S TRUNC_W_S ROUND_W_S ROUND_L_S FLOOR_W_S FLOOR_L_S
       // CEIL_W_S CEIL_L_S CVT_PS_S are unimplemented.
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterDRsType(Instruction* instr,
                                           const int32_t& fs_reg,
-                                          const int64_t& ft_reg,
+                                          const int32_t& ft_reg,
                                           const int32_t& fd_reg) {
-  double ft, fs;
+  double ft, fs, fd;
   uint32_t cc, fcsr_cc;
   fs = get_fpu_register_double(fs_reg);
   ft = get_fpu_register_double(ft_reg);
+  fd = get_fpu_register_double(fd_reg);
   cc = instr->FCccValue();
   fcsr_cc = get_fcsr_condition_bit(cc);
-  int64_t ft_int = static_cast<int64_t>(ft);
+  int64_t ft_int = bit_cast<int64_t>(ft);
+  int64_t fd_int = bit_cast<int64_t>(fd);
   switch (instr->FunctionFieldRaw()) {
+    case SEL:
+      DCHECK(kArchVariant == kMips64r6);
+      set_fpu_register_double(fd_reg, (fd_int & 0x1) == 0 ? fs : ft);
+      break;
     case SELEQZ_C:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_double(fd_reg, (ft_int & 0x1) == 0 ? fs : 0.0);
       break;
     case SELNEZ_C:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_double(fd_reg, (ft_int & 0x1) != 0 ? fs : 0.0);
       break;
+    case MIN:
+      DCHECK(kArchVariant == kMips64r6);
+      fs = get_fpu_register_double(fs_reg);
+      if (std::isnan(fs) && std::isnan(ft)) {
+        set_fpu_register_double(fd_reg, fs);
+      } else if (std::isnan(fs) && !std::isnan(ft)) {
+        set_fpu_register_double(fd_reg, ft);
+      } else if (!std::isnan(fs) && std::isnan(ft)) {
+        set_fpu_register_double(fd_reg, fs);
+      } else {
+        set_fpu_register_double(fd_reg, (fs >= ft) ? ft : fs);
+      }
+      break;
+    case MAX:
+      DCHECK(kArchVariant == kMips64r6);
+      fs = get_fpu_register_double(fs_reg);
+      if (std::isnan(fs) && std::isnan(ft)) {
+        set_fpu_register_double(fd_reg, fs);
+      } else if (std::isnan(fs) && !std::isnan(ft)) {
+        set_fpu_register_double(fd_reg, ft);
+      } else if (!std::isnan(fs) && std::isnan(ft)) {
+        set_fpu_register_double(fd_reg, fs);
+      } else {
+        set_fpu_register_double(fd_reg, (fs <= ft) ? ft : fs);
+      }
+      break;
     case ADD_D:
       set_fpu_register_double(fd_reg, fs + ft);
       break;
     case SUB_D:
       set_fpu_register_double(fd_reg, fs - ft);
       break;
     case MUL_D:
       set_fpu_register_double(fd_reg, fs * ft);
       break;
     case DIV_D:
@@ skipping 218 matching lines @@
         set_fpu_register(fd_reg, 0);
       }
       break;
     default:  // CMP_OR CMP_UNE CMP_NE UNIMPLEMENTED
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterCOP1(
-    Instruction* instr, const int64_t& rs_reg, const int64_t& rs,
-    const uint64_t& rs_u, const int64_t& rt_reg, const int64_t& rt,
-    const uint64_t& rt_u, const int64_t& rd_reg, const int32_t& fr_reg,
-    const int32_t& fs_reg, const int32_t& ft_reg, const int64_t& fd_reg,
+    Instruction* instr, const int32_t& rs_reg, const int64_t& rs,
+    const uint64_t& rs_u, const int32_t& rt_reg, const int64_t& rt,
+    const uint64_t& rt_u, const int32_t& rd_reg, const int32_t& fr_reg,
+    const int32_t& fs_reg, const int32_t& ft_reg, const int32_t& fd_reg,
     int64_t& alu_out) {
   switch (instr->RsFieldRaw()) {
     case BC1:  // Branch on coprocessor condition.
     case BC1EQZ:
     case BC1NEZ:
       UNREACHABLE();
       break;
     case CFC1:
       set_register(rt_reg, alu_out);
       break;
@@ skipping 33 matching lines @@
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterCOP1X(Instruction* instr,
                                         const int32_t& fr_reg,
                                         const int32_t& fs_reg,
                                         const int32_t& ft_reg,
-                                        const int64_t& fd_reg) {
+                                        const int32_t& fd_reg) {
   switch (instr->FunctionFieldRaw()) {
     case MADD_D:
       double fr, ft, fs;
       fr = get_fpu_register_double(fr_reg);
       fs = get_fpu_register_double(fs_reg);
       ft = get_fpu_register_double(ft_reg);
       set_fpu_register_double(fd_reg, fs * ft + fr);
       break;
     default:
       UNREACHABLE();
@@ skipping 213 matching lines @@
   // Instruction fields.
   const Opcode   op     = instr->OpcodeFieldRaw();
   const int64_t  rs_reg = instr->RsValue();
   const int64_t  rs     = get_register(rs_reg);
   const uint64_t rs_u   = static_cast<uint32_t>(rs);
   const int64_t  rt_reg = instr->RtValue();
   const int64_t  rt     = get_register(rt_reg);
   const uint64_t rt_u   = static_cast<uint32_t>(rt);
   const int64_t  rd_reg = instr->RdValue();
 
-  const int32_t  fr_reg = instr->FrValue();
-  const int32_t  fs_reg = instr->FsValue();
-  const int32_t  ft_reg = instr->FtValue();
-  const int64_t  fd_reg = instr->FdValue();
+  const int32_t fr_reg = instr->FrValue();
+  const int32_t fs_reg = instr->FsValue();
+  const int32_t ft_reg = instr->FtValue();
+  const int32_t fd_reg = instr->FdValue();
   int64_t  i64hilo = 0;
   uint64_t u64hilo = 0;
 
   // ALU output.
   // It should not be used as is. Instructions using it should always
   // initialize it first.
   int64_t alu_out = 0x12345678;
 
   // For break and trap instructions.
   bool do_interrupt = false;
@@ skipping 688 matching lines @@
 }
 
 
 #undef UNSUPPORTED
 
 } }  // namespace v8::internal
 
 #endif  // USE_SIMULATOR
 
 #endif  // V8_TARGET_ARCH_MIPS64