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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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2110 } | 2110 } |
2111 | 2111 |
2112 | 2112 |
2113 void Assembler::movf(Register rd, Register rs, uint16_t cc) { | 2113 void Assembler::movf(Register rd, Register rs, uint16_t cc) { |
2114 Register rt; | 2114 Register rt; |
2115 rt.code_ = (cc & 0x0007) << 2 | 0; | 2115 rt.code_ = (cc & 0x0007) << 2 | 0; |
2116 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); | 2116 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); |
2117 } | 2117 } |
2118 | 2118 |
2119 | 2119 |
2120 void Assembler::sel(SecondaryField fmt, FPURegister fd, | 2120 void Assembler::sel(SecondaryField fmt, FPURegister fd, FPURegister fs, |
2121 FPURegister ft, FPURegister fs, uint8_t sel) { | 2121 FPURegister ft) { |
2122 DCHECK(kArchVariant == kMips64r6); | 2122 DCHECK(kArchVariant == kMips64r6); |
2123 DCHECK(fmt == D); | 2123 DCHECK((fmt == D) || (fmt == S)); |
2124 DCHECK(fmt == S); | |
2125 | 2124 |
2126 Instr instr = COP1 | fmt << kRsShift | ft.code() << kFtShift | | 2125 Instr instr = COP1 | fmt << kRsShift | ft.code() << kFtShift | |
2127 fs.code() << kFsShift | fd.code() << kFdShift | SEL; | 2126 fs.code() << kFsShift | fd.code() << kFdShift | SEL; |
2128 emit(instr); | 2127 emit(instr); |
2129 } | 2128 } |
2130 | 2129 |
2131 | 2130 |
| 2131 void Assembler::max(SecondaryField fmt, FPURegister fd, FPURegister fs, |
| 2132 FPURegister ft) { |
| 2133 DCHECK(kArchVariant == kMips64r6); |
| 2134 DCHECK((fmt == D) || (fmt == S)); |
| 2135 GenInstrRegister(COP1, fmt, ft, fs, fd, MAX); |
| 2136 } |
| 2137 |
| 2138 |
| 2139 void Assembler::min(SecondaryField fmt, FPURegister fd, FPURegister fs, |
| 2140 FPURegister ft) { |
| 2141 DCHECK(kArchVariant == kMips64r6); |
| 2142 DCHECK((fmt == D) || (fmt == S)); |
| 2143 GenInstrRegister(COP1, fmt, ft, fs, fd, MIN); |
| 2144 } |
| 2145 |
| 2146 |
2132 // GPR. | 2147 // GPR. |
2133 void Assembler::seleqz(Register rs, Register rt, Register rd) { | 2148 void Assembler::seleqz(Register rd, Register rs, Register rt) { |
2134 DCHECK(kArchVariant == kMips64r6); | 2149 DCHECK(kArchVariant == kMips64r6); |
2135 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELEQZ_S); | 2150 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELEQZ_S); |
2136 } | 2151 } |
2137 | 2152 |
2138 | 2153 |
2139 // FPR. | 2154 // FPR. |
2140 void Assembler::seleqz(SecondaryField fmt, FPURegister fd, | 2155 void Assembler::seleqz(SecondaryField fmt, FPURegister fd, FPURegister fs, |
2141 FPURegister ft, FPURegister fs) { | 2156 FPURegister ft) { |
2142 DCHECK((fmt == D) || (fmt == S)); | 2157 DCHECK((fmt == D) || (fmt == S)); |
2143 GenInstrRegister(COP1, fmt, ft, fs, fd, SELEQZ_C); | 2158 GenInstrRegister(COP1, fmt, ft, fs, fd, SELEQZ_C); |
2144 } | 2159 } |
2145 | 2160 |
2146 | 2161 |
2147 // GPR. | 2162 // GPR. |
2148 void Assembler::selnez(Register rs, Register rt, Register rd) { | 2163 void Assembler::selnez(Register rd, Register rs, Register rt) { |
2149 DCHECK(kArchVariant == kMips64r6); | 2164 DCHECK(kArchVariant == kMips64r6); |
2150 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELNEZ_S); | 2165 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELNEZ_S); |
2151 } | 2166 } |
2152 | 2167 |
2153 | 2168 |
2154 // FPR. | 2169 // FPR. |
2155 void Assembler::selnez(SecondaryField fmt, FPURegister fd, | 2170 void Assembler::selnez(SecondaryField fmt, FPURegister fd, FPURegister fs, |
2156 FPURegister ft, FPURegister fs) { | 2171 FPURegister ft) { |
2157 DCHECK(kArchVariant == kMips64r6); | 2172 DCHECK(kArchVariant == kMips64r6); |
2158 DCHECK((fmt == D) || (fmt == S)); | 2173 DCHECK((fmt == D) || (fmt == S)); |
2159 GenInstrRegister(COP1, fmt, ft, fs, fd, SELNEZ_C); | 2174 GenInstrRegister(COP1, fmt, ft, fs, fd, SELNEZ_C); |
2160 } | 2175 } |
2161 | 2176 |
2162 | 2177 |
2163 // Bit twiddling. | 2178 // Bit twiddling. |
2164 void Assembler::clz(Register rd, Register rs) { | 2179 void Assembler::clz(Register rd, Register rs) { |
2165 if (kArchVariant != kMips64r6) { | 2180 if (kArchVariant != kMips64r6) { |
2166 // Clz instr requires same GPR number in 'rd' and 'rt' fields. | 2181 // Clz instr requires same GPR number in 'rd' and 'rt' fields. |
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2452 void Assembler::ceil_l_s(FPURegister fd, FPURegister fs) { | 2467 void Assembler::ceil_l_s(FPURegister fd, FPURegister fs) { |
2453 GenInstrRegister(COP1, S, f0, fs, fd, CEIL_L_S); | 2468 GenInstrRegister(COP1, S, f0, fs, fd, CEIL_L_S); |
2454 } | 2469 } |
2455 | 2470 |
2456 | 2471 |
2457 void Assembler::ceil_l_d(FPURegister fd, FPURegister fs) { | 2472 void Assembler::ceil_l_d(FPURegister fd, FPURegister fs) { |
2458 GenInstrRegister(COP1, D, f0, fs, fd, CEIL_L_D); | 2473 GenInstrRegister(COP1, D, f0, fs, fd, CEIL_L_D); |
2459 } | 2474 } |
2460 | 2475 |
2461 | 2476 |
2462 void Assembler::min(SecondaryField fmt, FPURegister fd, FPURegister ft, | |
2463 FPURegister fs) { | |
2464 DCHECK(kArchVariant == kMips64r6); | |
2465 DCHECK((fmt == D) || (fmt == S)); | |
2466 GenInstrRegister(COP1, fmt, ft, fs, fd, MIN); | |
2467 } | |
2468 | |
2469 | |
2470 void Assembler::mina(SecondaryField fmt, FPURegister fd, FPURegister ft, | 2477 void Assembler::mina(SecondaryField fmt, FPURegister fd, FPURegister ft, |
2471 FPURegister fs) { | 2478 FPURegister fs) { |
2472 DCHECK(kArchVariant == kMips64r6); | 2479 DCHECK(kArchVariant == kMips64r6); |
2473 DCHECK((fmt == D) || (fmt == S)); | 2480 DCHECK((fmt == D) || (fmt == S)); |
2474 GenInstrRegister(COP1, fmt, ft, fs, fd, MINA); | 2481 GenInstrRegister(COP1, fmt, ft, fs, fd, MINA); |
2475 } | 2482 } |
2476 | 2483 |
2477 | 2484 |
2478 void Assembler::max(SecondaryField fmt, FPURegister fd, FPURegister ft, | |
2479 FPURegister fs) { | |
2480 DCHECK(kArchVariant == kMips64r6); | |
2481 DCHECK((fmt == D) || (fmt == S)); | |
2482 GenInstrRegister(COP1, fmt, ft, fs, fd, MAX); | |
2483 } | |
2484 | |
2485 | |
2486 void Assembler::maxa(SecondaryField fmt, FPURegister fd, FPURegister ft, | 2485 void Assembler::maxa(SecondaryField fmt, FPURegister fd, FPURegister ft, |
2487 FPURegister fs) { | 2486 FPURegister fs) { |
2488 DCHECK(kArchVariant == kMips64r6); | 2487 DCHECK(kArchVariant == kMips64r6); |
2489 DCHECK((fmt == D) || (fmt == S)); | 2488 DCHECK((fmt == D) || (fmt == S)); |
2490 GenInstrRegister(COP1, fmt, ft, fs, fd, MAXA); | 2489 GenInstrRegister(COP1, fmt, ft, fs, fd, MAXA); |
2491 } | 2490 } |
2492 | 2491 |
2493 | 2492 |
2494 void Assembler::cvt_s_w(FPURegister fd, FPURegister fs) { | 2493 void Assembler::cvt_s_w(FPURegister fd, FPURegister fs) { |
2495 GenInstrRegister(COP1, W, f0, fs, fd, CVT_S_W); | 2494 GenInstrRegister(COP1, W, f0, fs, fd, CVT_S_W); |
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2960 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) { | 2959 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) { |
2961 // No out-of-line constant pool support. | 2960 // No out-of-line constant pool support. |
2962 DCHECK(!FLAG_enable_ool_constant_pool); | 2961 DCHECK(!FLAG_enable_ool_constant_pool); |
2963 return; | 2962 return; |
2964 } | 2963 } |
2965 | 2964 |
2966 | 2965 |
2967 } } // namespace v8::internal | 2966 } } // namespace v8::internal |
2968 | 2967 |
2969 #endif // V8_TARGET_ARCH_MIPS64 | 2968 #endif // V8_TARGET_ARCH_MIPS64 |
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