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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <limits.h> | 5 #include <limits.h> |
6 #include <stdarg.h> | 6 #include <stdarg.h> |
7 #include <stdlib.h> | 7 #include <stdlib.h> |
8 #include <cmath> | 8 #include <cmath> |
9 | 9 |
10 #include "src/v8.h" | 10 #include "src/v8.h" |
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2130 UNREACHABLE(); | 2130 UNREACHABLE(); |
2131 } | 2131 } |
2132 } | 2132 } |
2133 | 2133 |
2134 | 2134 |
2135 void Simulator::DecodeTypeRegisterDRsType(Instruction* instr, | 2135 void Simulator::DecodeTypeRegisterDRsType(Instruction* instr, |
2136 const int32_t& fr_reg, | 2136 const int32_t& fr_reg, |
2137 const int32_t& fs_reg, | 2137 const int32_t& fs_reg, |
2138 const int32_t& ft_reg, | 2138 const int32_t& ft_reg, |
2139 const int32_t& fd_reg) { | 2139 const int32_t& fd_reg) { |
2140 double ft, fs; | 2140 double ft, fs, fd; |
2141 uint32_t cc, fcsr_cc; | 2141 uint32_t cc, fcsr_cc; |
2142 int64_t i64; | 2142 int64_t i64; |
2143 fs = get_fpu_register_double(fs_reg); | 2143 fs = get_fpu_register_double(fs_reg); |
2144 ft = get_fpu_register_double(ft_reg); | 2144 ft = get_fpu_register_double(ft_reg); |
2145 int64_t ft_int = static_cast<int64_t>(ft); | 2145 int64_t ft_int = bit_cast<int64_t>(ft); |
| 2146 int64_t fd_int = bit_cast<int64_t>(fd); |
2146 cc = instr->FCccValue(); | 2147 cc = instr->FCccValue(); |
2147 fcsr_cc = get_fcsr_condition_bit(cc); | 2148 fcsr_cc = get_fcsr_condition_bit(cc); |
2148 switch (instr->FunctionFieldRaw()) { | 2149 switch (instr->FunctionFieldRaw()) { |
| 2150 case SEL: |
| 2151 DCHECK(IsMipsArchVariant(kMips32r6)); |
| 2152 set_fpu_register_double(fd_reg, (fd_int & 0x1) == 0 ? fs : ft); |
| 2153 break; |
2149 case SELEQZ_C: | 2154 case SELEQZ_C: |
2150 DCHECK(IsMipsArchVariant(kMips32r6)); | 2155 DCHECK(IsMipsArchVariant(kMips32r6)); |
2151 set_fpu_register_double(fd_reg, (ft_int & 0x1) == 0 ? fs : 0.0); | 2156 set_fpu_register_double(fd_reg, (ft_int & 0x1) == 0 ? fs : 0.0); |
2152 break; | 2157 break; |
2153 case SELNEZ_C: | 2158 case SELNEZ_C: |
2154 DCHECK(IsMipsArchVariant(kMips32r6)); | 2159 DCHECK(IsMipsArchVariant(kMips32r6)); |
2155 set_fpu_register_double(fd_reg, (ft_int & 0x1) != 0 ? fs : 0.0); | 2160 set_fpu_register_double(fd_reg, (ft_int & 0x1) != 0 ? fs : 0.0); |
2156 break; | 2161 break; |
| 2162 case MIN: |
| 2163 DCHECK(IsMipsArchVariant(kMips32r6)); |
| 2164 fs = get_fpu_register_double(fs_reg); |
| 2165 if (std::isnan(fs) && std::isnan(ft)) { |
| 2166 set_fpu_register_double(fd_reg, fs); |
| 2167 } else if (std::isnan(fs) && !std::isnan(ft)) { |
| 2168 set_fpu_register_double(fd_reg, ft); |
| 2169 } else if (!std::isnan(fs) && std::isnan(ft)) { |
| 2170 set_fpu_register_double(fd_reg, fs); |
| 2171 } else { |
| 2172 set_fpu_register_double(fd_reg, (fs >= ft) ? ft : fs); |
| 2173 } |
| 2174 break; |
| 2175 case MAX: |
| 2176 DCHECK(IsMipsArchVariant(kMips32r6)); |
| 2177 fs = get_fpu_register_double(fs_reg); |
| 2178 if (std::isnan(fs) && std::isnan(ft)) { |
| 2179 set_fpu_register_double(fd_reg, fs); |
| 2180 } else if (std::isnan(fs) && !std::isnan(ft)) { |
| 2181 set_fpu_register_double(fd_reg, ft); |
| 2182 } else if (!std::isnan(fs) && std::isnan(ft)) { |
| 2183 set_fpu_register_double(fd_reg, fs); |
| 2184 } else { |
| 2185 set_fpu_register_double(fd_reg, (fs <= ft) ? ft : fs); |
| 2186 } |
| 2187 break; |
| 2188 break; |
2157 case ADD_D: | 2189 case ADD_D: |
2158 set_fpu_register_double(fd_reg, fs + ft); | 2190 set_fpu_register_double(fd_reg, fs + ft); |
2159 break; | 2191 break; |
2160 case SUB_D: | 2192 case SUB_D: |
2161 set_fpu_register_double(fd_reg, fs - ft); | 2193 set_fpu_register_double(fd_reg, fs - ft); |
2162 break; | 2194 break; |
2163 case MUL_D: | 2195 case MUL_D: |
2164 set_fpu_register_double(fd_reg, fs * ft); | 2196 set_fpu_register_double(fd_reg, fs * ft); |
2165 break; | 2197 break; |
2166 case DIV_D: | 2198 case DIV_D: |
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3410 } | 3442 } |
3411 | 3443 |
3412 | 3444 |
3413 #undef UNSUPPORTED | 3445 #undef UNSUPPORTED |
3414 | 3446 |
3415 } } // namespace v8::internal | 3447 } } // namespace v8::internal |
3416 | 3448 |
3417 #endif // USE_SIMULATOR | 3449 #endif // USE_SIMULATOR |
3418 | 3450 |
3419 #endif // V8_TARGET_ARCH_MIPS | 3451 #endif // V8_TARGET_ARCH_MIPS |
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