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| 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 // All Rights Reserved. | 2 // All Rights Reserved. |
| 3 // | 3 // |
| 4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
| 5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
| 6 // met: | 6 // met: |
| 7 // | 7 // |
| 8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
| 9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
| 10 // | 10 // |
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| 197 | 197 |
| 198 Cell* RelocInfo::target_cell() { | 198 Cell* RelocInfo::target_cell() { |
| 199 DCHECK(rmode_ == RelocInfo::CELL); | 199 DCHECK(rmode_ == RelocInfo::CELL); |
| 200 return Cell::FromValueAddress(Memory::Address_at(pc_)); | 200 return Cell::FromValueAddress(Memory::Address_at(pc_)); |
| 201 } | 201 } |
| 202 | 202 |
| 203 | 203 |
| 204 void RelocInfo::set_target_cell(Cell* cell, | 204 void RelocInfo::set_target_cell(Cell* cell, |
| 205 WriteBarrierMode write_barrier_mode, | 205 WriteBarrierMode write_barrier_mode, |
| 206 ICacheFlushMode icache_flush_mode) { | 206 ICacheFlushMode icache_flush_mode) { |
| 207 DCHECK(cell->IsCell()); | |
| 208 DCHECK(rmode_ == RelocInfo::CELL); | 207 DCHECK(rmode_ == RelocInfo::CELL); |
| 209 Address address = cell->address() + Cell::kValueOffset; | 208 Address address = cell->address() + Cell::kValueOffset; |
| 210 Memory::Address_at(pc_) = address; | 209 Memory::Address_at(pc_) = address; |
| 211 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { | 210 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { |
| 212 CpuFeatures::FlushICache(pc_, sizeof(Address)); | 211 CpuFeatures::FlushICache(pc_, sizeof(Address)); |
| 213 } | 212 } |
| 214 if (write_barrier_mode == UPDATE_WRITE_BARRIER && host() != NULL) { | 213 if (write_barrier_mode == UPDATE_WRITE_BARRIER && host() != NULL) { |
| 215 // TODO(1550) We are passing NULL as a slot because cell can never be on | 214 // TODO(1550) We are passing NULL as a slot because cell can never be on |
| 216 // evacuation candidate. | 215 // evacuation candidate. |
| 217 host()->GetHeap()->incremental_marking()->RecordWrite( | 216 host()->GetHeap()->incremental_marking()->RecordWrite( |
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| 589 | 588 |
| 590 | 589 |
| 591 Operand::Operand(Immediate imm) { | 590 Operand::Operand(Immediate imm) { |
| 592 // [disp/r] | 591 // [disp/r] |
| 593 set_modrm(0, ebp); | 592 set_modrm(0, ebp); |
| 594 set_dispr(imm.x_, imm.rmode_); | 593 set_dispr(imm.x_, imm.rmode_); |
| 595 } | 594 } |
| 596 } } // namespace v8::internal | 595 } } // namespace v8::internal |
| 597 | 596 |
| 598 #endif // V8_IA32_ASSEMBLER_IA32_INL_H_ | 597 #endif // V8_IA32_ASSEMBLER_IA32_INL_H_ |
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