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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ | 5 #ifndef V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ |
6 #define V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ | 6 #define V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ |
7 | 7 |
8 namespace v8 { | 8 namespace v8 { |
9 namespace internal { | 9 namespace internal { |
10 namespace compiler { | 10 namespace compiler { |
11 | 11 |
12 // PPC-specific opcodes that specify which assembly sequence to emit. | 12 // PPC-specific opcodes that specify which assembly sequence to emit. |
13 // Most opcodes specify a single instruction. | 13 // Most opcodes specify a single instruction. |
14 #define TARGET_ARCH_OPCODE_LIST(V) \ | 14 #define TARGET_ARCH_OPCODE_LIST(V) \ |
15 V(PPC_And32) \ | 15 V(PPC_And) \ |
16 V(PPC_And64) \ | 16 V(PPC_AndComplement) \ |
17 V(PPC_AndComplement32) \ | 17 V(PPC_Or) \ |
18 V(PPC_AndComplement64) \ | 18 V(PPC_OrComplement) \ |
19 V(PPC_Or32) \ | 19 V(PPC_Xor) \ |
20 V(PPC_Or64) \ | |
21 V(PPC_OrComplement32) \ | |
22 V(PPC_OrComplement64) \ | |
23 V(PPC_Xor32) \ | |
24 V(PPC_Xor64) \ | |
25 V(PPC_ShiftLeft32) \ | 20 V(PPC_ShiftLeft32) \ |
26 V(PPC_ShiftLeft64) \ | 21 V(PPC_ShiftLeft64) \ |
27 V(PPC_ShiftRight32) \ | 22 V(PPC_ShiftRight32) \ |
28 V(PPC_ShiftRight64) \ | 23 V(PPC_ShiftRight64) \ |
29 V(PPC_ShiftRightAlg32) \ | 24 V(PPC_ShiftRightAlg32) \ |
30 V(PPC_ShiftRightAlg64) \ | 25 V(PPC_ShiftRightAlg64) \ |
31 V(PPC_RotRight32) \ | 26 V(PPC_RotRight32) \ |
32 V(PPC_RotRight64) \ | 27 V(PPC_RotRight64) \ |
33 V(PPC_Not32) \ | 28 V(PPC_Not) \ |
34 V(PPC_Not64) \ | |
35 V(PPC_RotLeftAndMask32) \ | 29 V(PPC_RotLeftAndMask32) \ |
36 V(PPC_RotLeftAndClear64) \ | 30 V(PPC_RotLeftAndClear64) \ |
37 V(PPC_RotLeftAndClearLeft64) \ | 31 V(PPC_RotLeftAndClearLeft64) \ |
38 V(PPC_RotLeftAndClearRight64) \ | 32 V(PPC_RotLeftAndClearRight64) \ |
39 V(PPC_Add32) \ | 33 V(PPC_Add) \ |
40 V(PPC_AddWithOverflow32) \ | 34 V(PPC_AddWithOverflow32) \ |
41 V(PPC_Add64) \ | 35 V(PPC_AddDouble) \ |
42 V(PPC_AddFloat64) \ | 36 V(PPC_Sub) \ |
43 V(PPC_Sub32) \ | |
44 V(PPC_SubWithOverflow32) \ | 37 V(PPC_SubWithOverflow32) \ |
45 V(PPC_Sub64) \ | 38 V(PPC_SubDouble) \ |
46 V(PPC_SubFloat64) \ | |
47 V(PPC_Mul32) \ | 39 V(PPC_Mul32) \ |
48 V(PPC_Mul64) \ | 40 V(PPC_Mul64) \ |
49 V(PPC_MulHigh32) \ | 41 V(PPC_MulHigh32) \ |
50 V(PPC_MulHighU32) \ | 42 V(PPC_MulHighU32) \ |
51 V(PPC_MulFloat64) \ | 43 V(PPC_MulDouble) \ |
52 V(PPC_Div32) \ | 44 V(PPC_Div32) \ |
53 V(PPC_Div64) \ | 45 V(PPC_Div64) \ |
54 V(PPC_DivU32) \ | 46 V(PPC_DivU32) \ |
55 V(PPC_DivU64) \ | 47 V(PPC_DivU64) \ |
56 V(PPC_DivFloat64) \ | 48 V(PPC_DivDouble) \ |
57 V(PPC_Mod32) \ | 49 V(PPC_Mod32) \ |
58 V(PPC_Mod64) \ | 50 V(PPC_Mod64) \ |
59 V(PPC_ModU32) \ | 51 V(PPC_ModU32) \ |
60 V(PPC_ModU64) \ | 52 V(PPC_ModU64) \ |
61 V(PPC_ModFloat64) \ | 53 V(PPC_ModDouble) \ |
62 V(PPC_Neg32) \ | 54 V(PPC_Neg) \ |
63 V(PPC_Neg64) \ | 55 V(PPC_NegDouble) \ |
64 V(PPC_NegFloat64) \ | 56 V(PPC_SqrtDouble) \ |
65 V(PPC_SqrtFloat64) \ | 57 V(PPC_FloorDouble) \ |
66 V(PPC_FloorFloat64) \ | 58 V(PPC_CeilDouble) \ |
67 V(PPC_CeilFloat64) \ | 59 V(PPC_TruncateDouble) \ |
68 V(PPC_TruncateFloat64) \ | 60 V(PPC_RoundDouble) \ |
69 V(PPC_RoundFloat64) \ | 61 V(PPC_MaxDouble) \ |
70 V(PPC_MaxFloat64) \ | 62 V(PPC_MinDouble) \ |
71 V(PPC_MinFloat64) \ | |
72 V(PPC_Cntlz32) \ | 63 V(PPC_Cntlz32) \ |
73 V(PPC_Cmp32) \ | 64 V(PPC_Cmp32) \ |
74 V(PPC_Cmp64) \ | 65 V(PPC_Cmp64) \ |
75 V(PPC_CmpFloat64) \ | 66 V(PPC_CmpDouble) \ |
76 V(PPC_Tst32) \ | 67 V(PPC_Tst32) \ |
77 V(PPC_Tst64) \ | 68 V(PPC_Tst64) \ |
78 V(PPC_Push) \ | 69 V(PPC_Push) \ |
79 V(PPC_ExtendSignWord8) \ | 70 V(PPC_ExtendSignWord8) \ |
80 V(PPC_ExtendSignWord16) \ | 71 V(PPC_ExtendSignWord16) \ |
81 V(PPC_ExtendSignWord32) \ | 72 V(PPC_ExtendSignWord32) \ |
82 V(PPC_Uint32ToUint64) \ | 73 V(PPC_Uint32ToUint64) \ |
83 V(PPC_Int64ToInt32) \ | 74 V(PPC_Int64ToInt32) \ |
84 V(PPC_Int32ToFloat64) \ | 75 V(PPC_Int32ToDouble) \ |
85 V(PPC_Uint32ToFloat64) \ | 76 V(PPC_Uint32ToDouble) \ |
86 V(PPC_Float32ToFloat64) \ | 77 V(PPC_Float32ToDouble) \ |
87 V(PPC_Float64ToInt32) \ | 78 V(PPC_DoubleToInt32) \ |
88 V(PPC_Float64ToUint32) \ | 79 V(PPC_DoubleToUint32) \ |
89 V(PPC_Float64ToFloat32) \ | 80 V(PPC_DoubleToFloat32) \ |
90 V(PPC_Float64ExtractLowWord32) \ | 81 V(PPC_DoubleExtractLowWord32) \ |
91 V(PPC_Float64ExtractHighWord32) \ | 82 V(PPC_DoubleExtractHighWord32) \ |
92 V(PPC_Float64InsertLowWord32) \ | 83 V(PPC_DoubleInsertLowWord32) \ |
93 V(PPC_Float64InsertHighWord32) \ | 84 V(PPC_DoubleInsertHighWord32) \ |
94 V(PPC_Float64Construct) \ | 85 V(PPC_DoubleConstruct) \ |
95 V(PPC_LoadWordS8) \ | 86 V(PPC_LoadWordS8) \ |
96 V(PPC_LoadWordU8) \ | 87 V(PPC_LoadWordU8) \ |
97 V(PPC_LoadWordS16) \ | 88 V(PPC_LoadWordS16) \ |
98 V(PPC_LoadWordU16) \ | 89 V(PPC_LoadWordU16) \ |
99 V(PPC_LoadWordS32) \ | 90 V(PPC_LoadWordS32) \ |
100 V(PPC_LoadWord64) \ | 91 V(PPC_LoadWord64) \ |
101 V(PPC_LoadFloat32) \ | 92 V(PPC_LoadFloat32) \ |
102 V(PPC_LoadFloat64) \ | 93 V(PPC_LoadDouble) \ |
103 V(PPC_StoreWord8) \ | 94 V(PPC_StoreWord8) \ |
104 V(PPC_StoreWord16) \ | 95 V(PPC_StoreWord16) \ |
105 V(PPC_StoreWord32) \ | 96 V(PPC_StoreWord32) \ |
106 V(PPC_StoreWord64) \ | 97 V(PPC_StoreWord64) \ |
107 V(PPC_StoreFloat32) \ | 98 V(PPC_StoreFloat32) \ |
108 V(PPC_StoreFloat64) \ | 99 V(PPC_StoreDouble) \ |
109 V(PPC_StoreWriteBarrier) | 100 V(PPC_StoreWriteBarrier) |
110 | 101 |
111 | 102 |
112 // Addressing modes represent the "shape" of inputs to an instruction. | 103 // Addressing modes represent the "shape" of inputs to an instruction. |
113 // Many instructions support multiple addressing modes. Addressing modes | 104 // Many instructions support multiple addressing modes. Addressing modes |
114 // are encoded into the InstructionCode of the instruction and tell the | 105 // are encoded into the InstructionCode of the instruction and tell the |
115 // code generator after register allocation which assembler method to call. | 106 // code generator after register allocation which assembler method to call. |
116 // | 107 // |
117 // We use the following local notation for addressing modes: | 108 // We use the following local notation for addressing modes: |
118 // | 109 // |
119 // R = register | 110 // R = register |
120 // O = register or stack slot | 111 // O = register or stack slot |
121 // D = double register | 112 // D = double register |
122 // I = immediate (handle, external, int32) | 113 // I = immediate (handle, external, int32) |
123 // MRI = [register + immediate] | 114 // MRI = [register + immediate] |
124 // MRR = [register + register] | 115 // MRR = [register + register] |
125 #define TARGET_ADDRESSING_MODE_LIST(V) \ | 116 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
126 V(MRI) /* [%r0 + K] */ \ | 117 V(MRI) /* [%r0 + K] */ \ |
127 V(MRR) /* [%r0 + %r1] */ | 118 V(MRR) /* [%r0 + %r1] */ |
128 | 119 |
129 } // namespace compiler | 120 } // namespace compiler |
130 } // namespace internal | 121 } // namespace internal |
131 } // namespace v8 | 122 } // namespace v8 |
132 | 123 |
133 #endif // V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ | 124 #endif // V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ |
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