Finish 'MIPS: [turbofan] Add backend support for float32 operations.'

test/cctest/test-assembler-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 28 matching lines @@
 
 
 using namespace v8::internal;
 
 
 // Define these function prototypes to match JSEntryFunction in execution.cc.
 typedef Object* (*F1)(int x, int p1, int p2, int p3, int p4);
 typedef Object* (*F2)(int x, int y, int p2, int p3, int p4);
 typedef Object* (*F3)(void* p, int p1, int p2, int p3, int p4);
 
+// clang-format off

[jochen (gone - plz use gerrit), 2015/11/25 13:00:26]

please don't do this. clang-format off is meant to be used a small scope, not a
blanket thing for the entire file.

+
 
 #define __ assm.
 TEST(MIPS16) {
   CcTest::InitializeVM();
   Isolate* isolate = CcTest::i_isolate();
   HandleScope scope(isolate);
   MacroAssembler assm(isolate, NULL, 0);
 
   typedef struct test {
     int a;
@@ skipping 281 matching lines @@
   typedef struct {
     double a;
     double b;
     double c;
     double d;
     double e;
     double f;
     double g;
     double h;
     double i;
+    float fa;
+    float fb;
+    float fc;
+    float fd;
+    float fe;
+    float ff;
+    float fg;
   } T;
   T t;
 
   // Create a function that accepts &t, and loads, manipulates, and stores
   // the doubles t.a ... t.f.
   MacroAssembler assm(isolate, NULL, 0);
   Label L, C;
 
+  // Double precision floating point instructions.
   __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
   __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
   __ add_d(f8, f4, f6);
   __ sdc1(f8, MemOperand(a0, OFFSET_OF(T, c)) );  // c = a + b.
 
   __ mov_d(f10, f8);  // c
   __ neg_d(f12, f6);  // -b
   __ sub_d(f10, f10, f12);
   __ sdc1(f10, MemOperand(a0, OFFSET_OF(T, d)) );  // d = c - (-b).
 
@@ skipping 12 matching lines @@
   __ sdc1(f14, MemOperand(a0, OFFSET_OF(T, g)) );
   // g = sqrt(f) = 10.97451593465515908537
 
   if (IsMipsArchVariant(kMips32r2)) {
     __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, h)) );
     __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, i)) );
     __ madd_d(f14, f6, f4, f6);
     __ sdc1(f14, MemOperand(a0, OFFSET_OF(T, h)) );
   }
 
+  // Single precision floating point instructions.
+  __ lwc1(f4, MemOperand(a0, OFFSET_OF(T, fa)) );
+  __ lwc1(f6, MemOperand(a0, OFFSET_OF(T, fb)) );
+  __ add_s(f8, f4, f6);
+  __ swc1(f8, MemOperand(a0, OFFSET_OF(T, fc)) );  // fc = fa + fb.
+
+  __ neg_s(f10, f6);  // -fb
+  __ sub_s(f10, f8, f10);
+  __ swc1(f10, MemOperand(a0, OFFSET_OF(T, fd)) );  // fd = fc - (-fb).
+
+  __ swc1(f4, MemOperand(a0, OFFSET_OF(T, fb)) );   // fb = fa.
+
+  __ li(t0, 120);
+  __ mtc1(t0, f14);
+  __ cvt_s_w(f14, f14);   // f14 = 120.0.
+  __ mul_s(f10, f10, f14);
+  __ swc1(f10, MemOperand(a0, OFFSET_OF(T, fe)) );  // fe = fd * 120
+
+  __ div_s(f12, f10, f4);
+  __ swc1(f12, MemOperand(a0, OFFSET_OF(T, ff)) );  // ff = fe / fa
+
+  __ sqrt_s(f14, f12);
+  __ swc1(f14, MemOperand(a0, OFFSET_OF(T, fg)) );
+
   __ jr(ra);
   __ nop();
 
   CodeDesc desc;
   assm.GetCode(&desc);
   Handle<Code> code = isolate->factory()->NewCode(
       desc, Code::ComputeFlags(Code::STUB), Handle<Code>());
   F3 f = FUNCTION_CAST<F3>(code->entry());
+  // Double test values.
   t.a = 1.5e14;
   t.b = 2.75e11;
   t.c = 0.0;
   t.d = 0.0;
   t.e = 0.0;
   t.f = 0.0;
   t.h = 1.5;
   t.i = 2.75;
+  // Single test values.
+  t.fa = 1.5e6;
+  t.fb = 2.75e4;
+  t.fc = 0.0;
+  t.fd = 0.0;
+  t.fe = 0.0;
+  t.ff = 0.0;
   Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
   USE(dummy);
+  // Expected double results.
   CHECK_EQ(1.5e14, t.a);
   CHECK_EQ(1.5e14, t.b);
   CHECK_EQ(1.50275e14, t.c);
   CHECK_EQ(1.50550e14, t.d);
   CHECK_EQ(1.8066e16, t.e);
   CHECK_EQ(120.44, t.f);
   CHECK_EQ(10.97451593465515908537, t.g);
   if (IsMipsArchVariant(kMips32r2)) {
     CHECK_EQ(6.875, t.h);
   }
+  // Expected single results.
+  CHECK_EQ(1.5e6, t.fa);
+  CHECK_EQ(1.5e6, t.fb);
+  CHECK_EQ(1.5275e06, t.fc);
+  CHECK_EQ(1.5550e06, t.fd);
+  CHECK_EQ(1.866e08, t.fe);
+  CHECK_EQ(124.40000152587890625, t.ff);
+  CHECK_EQ(11.1534748077392578125, t.fg);
 }
 
 
 TEST(MIPS4) {
   // Test moves between floating point and integer registers.
   CcTest::InitializeVM();
   Isolate* isolate = CcTest::i_isolate();
   HandleScope scope(isolate);
 
   typedef struct {
@@ skipping 1140 matching lines @@
     ::printf("f(%d) = ", i);
     result->Print(std::cout);
     ::printf("\n");
 #endif
     CHECK(values[i].is_identical_to(result));
   }
 }
 
 
 #undef __