Finish 'MIPS: [turbofan] Add backend support for float32 operations.'

src/mips/disasm-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // A Disassembler object is used to disassemble a block of code instruction by
 // instruction. The default implementation of the NameConverter object can be
 // overriden to modify register names or to do symbol lookup on addresses.
 //
 // The example below will disassemble a block of code and print it to stdout.
 //
@@ skipping 71 matching lines @@
   void PrintBc(Instruction* instr);
   void PrintCc(Instruction* instr);
   void PrintFunction(Instruction* instr);
   void PrintSecondaryField(Instruction* instr);
   void PrintUImm16(Instruction* instr);
   void PrintSImm16(Instruction* instr);
   void PrintXImm16(Instruction* instr);
   void PrintXImm21(Instruction* instr);
   void PrintXImm26(Instruction* instr);
   void PrintCode(Instruction* instr);   // For break and trap instructions.
+  void PrintFormat(Instruction* instr);  // For floating format postfix.
   // Printing of instruction name.
   void PrintInstructionName(Instruction* instr);
 
   // Handle formatting of instructions and their options.
   int FormatRegister(Instruction* instr, const char* option);
   int FormatFPURegister(Instruction* instr, const char* option);
   int FormatOption(Instruction* instr, const char* option);
   void Format(Instruction* instr, const char* format);
   void Unknown(Instruction* instr);
 
 
   // Each of these functions decodes one particular instruction type.
+  bool DecodeTypeRegisterRsType(Instruction* instr);
+  void DecodeTypeRegisterSRsType(Instruction* instr);
   void DecodeTypeRegisterDRsType(Instruction* instr);
   void DecodeTypeRegisterLRsType(Instruction* instr);
   void DecodeTypeRegisterSPECIAL(Instruction* instr);
   void DecodeTypeRegisterSPECIAL2(Instruction* instr);
   void DecodeTypeRegisterSPECIAL3(Instruction* instr);
   void DecodeTypeRegister(Instruction* instr);
   void DecodeTypeImmediate(Instruction* instr);
   void DecodeTypeJump(Instruction* instr);
 
   const disasm::NameConverter& converter_;
@@ skipping 174 matching lines @@
       out_buffer_pos_ +=
           SNPrintF(out_buffer_ + out_buffer_pos_, "0x%03x", code);
       break;
     }
     default:  // Not a break or trap instruction.
     break;
   }
 }
 
 
+void Decoder::PrintFormat(Instruction* instr) {
+  char formatLetter = ' ';
+  switch (instr->RsFieldRaw()) {
+    case S:
+      formatLetter = 's';
+      break;
+    case D:
+      formatLetter = 'd';
+      break;
+    case W:
+      formatLetter = 'w';
+      break;
+    case L:
+      formatLetter = 'l';
+      break;
+    default:
+      UNREACHABLE();
+      break;
+  }
+  PrintChar(formatLetter);
+}
+
+
 // Printing of instruction name.
 void Decoder::PrintInstructionName(Instruction* instr) {
 }
 
 
 // Handle all register based formatting in this function to reduce the
 // complexity of FormatOption.
 int Decoder::FormatRegister(Instruction* instr, const char* format) {
   DCHECK(format[0] == 'r');
   if (format[1] == 's') {  // 'rs: Rs register.
@@ skipping 110 matching lines @@
     case 'b': {   // 'bc - Special for bc1 cc field.
       DCHECK(STRING_STARTS_WITH(format, "bc"));
       PrintBc(instr);
       return 2;
     }
     case 'C': {   // 'Cc - Special for c.xx.d cc field.
       DCHECK(STRING_STARTS_WITH(format, "Cc"));
       PrintCc(instr);
       return 2;
     }
+    case 't':
+      PrintFormat(instr);
+      return 1;
   }
   UNREACHABLE();
   return -1;
 }
 
 
 // Format takes a formatting string for a whole instruction and prints it into
 // the output buffer. All escaped options are handed to FormatOption to be
 // parsed further.
 void Decoder::Format(Instruction* instr, const char* format) {
@@ skipping 10 matching lines @@
 }
 
 
 // For currently unimplemented decodings the disassembler calls Unknown(instr)
 // which will just print "unknown" of the instruction bits.
 void Decoder::Unknown(Instruction* instr) {
   Format(instr, "unknown");
 }
 
 
+bool Decoder::DecodeTypeRegisterRsType(Instruction* instr) {
+  switch (instr->FunctionFieldRaw()) {
+    case ADD_D:
+      Format(instr, "add.'t   'fd, 'fs, 'ft");
+      break;
+    case SUB_D:
+      Format(instr, "sub.'t   'fd, 'fs, 'ft");
+      break;
+    case MUL_D:
+      Format(instr, "mul.'t   'fd, 'fs, 'ft");
+      break;
+    case DIV_D:
+      Format(instr, "div.'t   'fd, 'fs, 'ft");
+      break;
+    case ABS_D:
+      Format(instr, "abs.'t   'fd, 'fs");
+      break;
+    case MOV_D:
+      Format(instr, "mov.'t   'fd, 'fs");
+      break;
+    case NEG_D:
+      Format(instr, "neg.'t   'fd, 'fs");
+      break;
+    case SQRT_D:
+      Format(instr, "sqrt.'t  'fd, 'fs");
+      break;
+    case CVT_W_D:
+      Format(instr, "cvt.w.'t 'fd, 'fs");
+      break;
+    case CVT_L_D:
+      Format(instr, "cvt.l.'t 'fd, 'fs");
+      break;
+    case TRUNC_W_D:
+      Format(instr, "trunc.w.'t 'fd, 'fs");
+      break;
+    case TRUNC_L_D:
+      Format(instr, "trunc.l.'t 'fd, 'fs");
+      break;
+    case ROUND_W_D:
+      Format(instr, "round.w.'t 'fd, 'fs");
+      break;
+    case FLOOR_W_D:
+      Format(instr, "floor.w.'t 'fd, 'fs");
+      break;
+    case CEIL_W_D:
+      Format(instr, "ceil.w.'t 'fd, 'fs");
+      break;
+    case CVT_S_D:
+      Format(instr, "cvt.s.'t 'fd, 'fs");
+      break;
+    case C_F_D:
+      Format(instr, "c.f.'t   'fs, 'ft, 'Cc");
+      break;
+    case C_UN_D:
+      Format(instr, "c.un.'t  'fs, 'ft, 'Cc");
+      break;
+    case C_EQ_D:
+      Format(instr, "c.eq.'t  'fs, 'ft, 'Cc");
+      break;
+    case C_UEQ_D:
+      Format(instr, "c.ueq.'t 'fs, 'ft, 'Cc");
+      break;
+    case C_OLT_D:
+      Format(instr, "c.olt.'t 'fs, 'ft, 'Cc");
+      break;
+    case C_ULT_D:
+      Format(instr, "c.ult.'t 'fs, 'ft, 'Cc");
+      break;
+    case C_OLE_D:
+      Format(instr, "c.ole.'t 'fs, 'ft, 'Cc");
+      break;
+    case C_ULE_D:
+      Format(instr, "c.ule.'t 'fs, 'ft, 'Cc");
+      break;
+    default:
+      return false;
+  }
+  return true;
+}
+
+
+void Decoder::DecodeTypeRegisterSRsType(Instruction* instr) {
+  if (!DecodeTypeRegisterRsType(instr)) {
+    switch (instr->FunctionFieldRaw()) {
+      case CVT_D_S:
+        Format(instr, "cvt.d.'t 'fd, 'fs");
+        break;
+      default:
+        Format(instr, "unknown.cop1.'t");
+        break;
+    }
+  }
+}
+
+
 void Decoder::DecodeTypeRegisterDRsType(Instruction* instr) {
-  switch (instr->FunctionFieldRaw()) {
-    case ADD_D:
-      Format(instr, "add.d   'fd, 'fs, 'ft");
-      break;
-    case SUB_D:
-      Format(instr, "sub.d   'fd, 'fs, 'ft");
-      break;
-    case MUL_D:
-      Format(instr, "mul.d   'fd, 'fs, 'ft");
-      break;
-    case DIV_D:
-      Format(instr, "div.d   'fd, 'fs, 'ft");
-      break;
-    case ABS_D:
-      Format(instr, "abs.d   'fd, 'fs");
-      break;
-    case MOV_D:
-      Format(instr, "mov.d   'fd, 'fs");
-      break;
-    case NEG_D:
-      Format(instr, "neg.d   'fd, 'fs");
-      break;
-    case SQRT_D:
-      Format(instr, "sqrt.d  'fd, 'fs");
-      break;
-    case CVT_W_D:
-      Format(instr, "cvt.w.d 'fd, 'fs");
-      break;
-    case CVT_L_D:
-      Format(instr, "cvt.l.d 'fd, 'fs");
-      break;
-    case TRUNC_W_D:
-      Format(instr, "trunc.w.d 'fd, 'fs");
-      break;
-    case TRUNC_L_D:
-      Format(instr, "trunc.l.d 'fd, 'fs");
-      break;
-    case ROUND_W_D:
-      Format(instr, "round.w.d 'fd, 'fs");
-      break;
-    case FLOOR_W_D:
-      Format(instr, "floor.w.d 'fd, 'fs");
-      break;
-    case CEIL_W_D:
-      Format(instr, "ceil.w.d 'fd, 'fs");
-      break;
-    case CVT_S_D:
-      Format(instr, "cvt.s.d 'fd, 'fs");
-      break;
-    case C_F_D:
-      Format(instr, "c.f.d   'fs, 'ft, 'Cc");
-      break;
-    case C_UN_D:
-      Format(instr, "c.un.d  'fs, 'ft, 'Cc");
-      break;
-    case C_EQ_D:
-      Format(instr, "c.eq.d  'fs, 'ft, 'Cc");
-      break;
-    case C_UEQ_D:
-      Format(instr, "c.ueq.d 'fs, 'ft, 'Cc");
-      break;
-    case C_OLT_D:
-      Format(instr, "c.olt.d 'fs, 'ft, 'Cc");
-      break;
-    case C_ULT_D:
-      Format(instr, "c.ult.d 'fs, 'ft, 'Cc");
-      break;
-    case C_OLE_D:
-      Format(instr, "c.ole.d 'fs, 'ft, 'Cc");
-      break;
-    case C_ULE_D:
-      Format(instr, "c.ule.d 'fs, 'ft, 'Cc");
-      break;
-    default:
-      Format(instr, "unknown.cop1.d");
-      break;
+  if (!DecodeTypeRegisterRsType(instr)) {
+    Format(instr, "unknown.cop1.'t");
   }
 }
 
 
 void Decoder::DecodeTypeRegisterLRsType(Instruction* instr) {
   switch (instr->FunctionFieldRaw()) {
     case CVT_D_L:
       Format(instr, "cvt.d.l 'fd, 'fs");
       break;
     case CVT_S_L:
@@ skipping 280 matching lines @@
         // These are called "fs" too, although they are not FPU registers.
         case CTC1:
           Format(instr, "ctc1    'rt, 'fs");
           break;
         case CFC1:
           Format(instr, "cfc1    'rt, 'fs");
           break;
         case MTHC1:
           Format(instr, "mthc1   'rt, 'fs");
           break;
+        case S:
+          DecodeTypeRegisterSRsType(instr);
+          break;
         case D:
           DecodeTypeRegisterDRsType(instr);
           break;
-        case S:
-          switch (instr->FunctionFieldRaw()) {
-            case CVT_D_S:
-              Format(instr, "cvt.d.s 'fd, 'fs");
-              break;
-            default:
-              UNIMPLEMENTED_MIPS();
-          }
-          break;
         case W:
           switch (instr->FunctionFieldRaw()) {
             case CVT_S_W:   // Convert word to float (single).
               Format(instr, "cvt.s.w 'fd, 'fs");
               break;
             case CVT_D_W:   // Convert word to double.
               Format(instr, "cvt.d.w 'fd, 'fs");
               break;
             default:
               UNREACHABLE();
@@ skipping 523 matching lines @@
         prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 #undef UNSUPPORTED
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_MIPS