MIPS: [turbofan] Add backend support for float32 operations.

src/mips/macro-assembler-mips.h

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
 #define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
 
 #include "src/assembler.h"
 #include "src/globals.h"
 #include "src/mips/assembler-mips.h"
@@ skipping 753 matching lines @@
   // the higher 32 bits of the 64-bit coprocessor register,
   // while leaving the low bits unchanged.
   void Mthc1(Register rt, FPURegister fs);
 
   // FP32 mode: move the high part of the double-register pair into
   // general purpose register.
   // FP64 mode: Move the higher 32 bits of the 64-bit coprocessor register into
   // general-purpose register.
   void Mfhc1(Register rt, FPURegister fs);
 
-  // Wrapper function for the different cmp/branch types.
+  // Wrapper functions for the different cmp/branch types.
+  void BranchFSize(SecondaryField sizeField, Label* target, Label* nan,
+                   Condition cc, FPURegister cmp1, FPURegister cmp2,
+                   BranchDelaySlot bd = PROTECT);
+
   void BranchF(Label* target,
                Label* nan,
                Condition cc,
                FPURegister cmp1,
                FPURegister cmp2,
                BranchDelaySlot bd = PROTECT);
 
+  void BranchFS(Label* target, Label* nan, Condition cc, FPURegister cmp1,
+                FPURegister cmp2, BranchDelaySlot bd = PROTECT);
+
   // Alternate (inline) version for better readability with USE_DELAY_SLOT.
   inline void BranchF(BranchDelaySlot bd,
                       Label* target,
                       Label* nan,
                       Condition cc,
                       FPURegister cmp1,
                       FPURegister cmp2) {
     BranchF(target, nan, cc, cmp1, cmp2, bd);
   }
 
+  inline void BranchFS(BranchDelaySlot bd, Label* target, Label* nan,
+                       Condition cc, FPURegister cmp1, FPURegister cmp2) {
+    BranchFS(target, nan, cc, cmp1, cmp2, bd);
+  }
+
   // Truncates a double using a specific rounding mode, and writes the value
   // to the result register.
   // The except_flag will contain any exceptions caused by the instruction.
   // If check_inexact is kDontCheckForInexactConversion, then the inexact
   // exception is masked.
   void EmitFPUTruncate(FPURoundingMode rounding_mode,
                        Register result,
                        DoubleRegister double_input,
                        Register scratch,
                        DoubleRegister double_scratch,
@@ skipping 912 matching lines @@
 #define CODE_COVERAGE_TOSTRING(x) CODE_COVERAGE_STRINGIFY(x)
 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__)
 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm->
 #else
 #define ACCESS_MASM(masm) masm->
 #endif
 
 } }  // namespace v8::internal
 
 #endif  // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_