[x64] Match -0 - x with sign bit flip.

src/compiler/x64/code-generator-x64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/code-generator.h"
 
 #include "src/compiler/code-generator-impl.h"
 #include "src/compiler/gap-resolver.h"
 #include "src/compiler/node-matchers.h"
 #include "src/scopes.h"
@@ skipping 708 matching lines @@
       break;
     case kSSEFloat32Sub:
       ASSEMBLE_SSE_BINOP(subss);
       break;
     case kSSEFloat32Mul:
       ASSEMBLE_SSE_BINOP(mulss);
       break;
     case kSSEFloat32Div:
       ASSEMBLE_SSE_BINOP(divss);
       break;
+    case kSSEFloat32Neg: {
+      // TODO(bmeurer): Use RIP relative 128-bit constants.
+      // TODO(turbofan): Add AVX version with relaxed register constraints.
+      __ pcmpeqd(kScratchDoubleReg, kScratchDoubleReg);
+      __ psllq(kScratchDoubleReg, 31);
+      __ xorps(i.OutputDoubleRegister(), kScratchDoubleReg);
+      break;
+    }
+    case kSSEFloat32Sqrt:
+      ASSEMBLE_SSE_UNOP(sqrtss);
+      break;
     case kSSEFloat32Max:
       ASSEMBLE_SSE_BINOP(maxss);
       break;
     case kSSEFloat32Min:
       ASSEMBLE_SSE_BINOP(minss);
       break;
-    case kSSEFloat32Sqrt:
-      ASSEMBLE_SSE_UNOP(sqrtss);
-      break;
     case kSSEFloat32ToFloat64:
       ASSEMBLE_SSE_UNOP(cvtss2sd);
       break;
     case kSSEFloat64Cmp:
       ASSEMBLE_SSE_BINOP(ucomisd);
       break;
     case kSSEFloat64Add:
       ASSEMBLE_SSE_BINOP(addsd);
       break;
     case kSSEFloat64Sub:
@@ skipping 36 matching lines @@
       __ movsd(i.OutputDoubleRegister(), Operand(rsp, 0));
       __ addq(rsp, Immediate(kDoubleSize));
       break;
     }
     case kSSEFloat64Max:
       ASSEMBLE_SSE_BINOP(maxsd);
       break;
     case kSSEFloat64Min:
       ASSEMBLE_SSE_BINOP(minsd);
       break;
+    case kSSEFloat64Neg: {
+      // TODO(bmeurer): Use RIP relative 128-bit constants.
+      // TODO(turbofan): Add AVX version with relaxed register constraints.
+      __ pcmpeqd(kScratchDoubleReg, kScratchDoubleReg);
+      __ psllq(kScratchDoubleReg, 63);
+      __ xorpd(i.OutputDoubleRegister(), kScratchDoubleReg);
+      break;
+    }
     case kSSEFloat64Sqrt:
       ASSEMBLE_SSE_UNOP(sqrtsd);
       break;
     case kSSEFloat64Round: {
       CpuFeatureScope sse_scope(masm(), SSE4_1);
       RoundingMode const mode =
           static_cast<RoundingMode>(MiscField::decode(instr->opcode()));
       __ roundsd(i.OutputDoubleRegister(), i.InputDoubleRegister(0), mode);
       break;
     }
@@ skipping 756 matching lines @@
     }
   }
   MarkLazyDeoptSite();
 }
 
 #undef __
 
 }  // namespace internal
 }  // namespace compiler
 }  // namespace v8