MIPS: Refactor simulator and add selection instructions for r6.

src/mips64/simulator-mips64.h

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 
 // Declares a Simulator for MIPS instructions if we are not generating a native
 // MIPS binary. This Simulator allows us to run and debug MIPS code generation
 // on regular desktop machines.
 // V8 calls into generated code by "calling" the CALL_GENERATED_CODE macro,
 // which will start execution in the Simulator or forwards to the real entry
@@ skipping 294 matching lines @@
   void TraceMemRd(int64_t addr, int64_t value);
 
   // Operations depending on endianness.
   // Get Double Higher / Lower word.
   inline int32_t GetDoubleHIW(double* addr);
   inline int32_t GetDoubleLOW(double* addr);
   // Set Double Higher / Lower word.
   inline int32_t SetDoubleHIW(double* addr);
   inline int32_t SetDoubleLOW(double* addr);
 
+  // functions called from DecodeTypeRegister
+  void DecodeTypeRegisterCOP1(Instruction* instr, const int64_t& rs_reg,
+                              const int64_t& rs, const uint64_t& rs_u,
+                              const int64_t& rt_reg, const int64_t& rt,
+                              const uint64_t& rt_u, const int64_t& rd_reg,
+                              const int32_t& fr_reg, const int32_t& fs_reg,
+                              const int32_t& ft_reg, const int64_t& fd_reg,
+                              int64_t& alu_out);
+
+  void DecodeTypeRegisterCOP1X(Instruction* instr, const int32_t& fr_reg,
+                               const int32_t& fs_reg, const int32_t& ft_reg,
+                               const int64_t& fd_reg);
+
+  void DecodeTypeRegisterSPECIAL(
+      Instruction* instr, const int64_t& rs_reg, const int64_t& rs,
+      const uint64_t& rs_u, const int64_t& rt_reg, const int64_t& rt,
+      const uint64_t& rt_u, const int64_t& rd_reg, const int32_t& fr_reg,
+      const int32_t& fs_reg, const int32_t& ft_reg, const int64_t& fd_reg,
+      int64_t& i64hilo, uint64_t& u64hilo, int64_t& alu_out, bool& do_interrupt,
+      int64_t& current_pc, int64_t& next_pc, int64_t& return_addr_reg,
+      int64_t& i128resultH, int64_t& i128resultL);
+
+  void DecodeTypeRegisterSPECIAL2(Instruction* instr, const int64_t& rd_reg,
+                                  int64_t& alu_out);
+
+  void DecodeTypeRegisterSPECIAL3(Instruction* instr, const int64_t& rt_reg,
+                                  int64_t& alu_out);
+
+  void DecodeTypeRegisterSRsType(Instruction* instr, const int32_t& fs_reg,
+                                 const int64_t& fd_reg);
+
+  void DecodeTypeRegisterDRsType(Instruction* instr, const int32_t& fs_reg,
+                                 const int64_t& ft_reg, const int32_t& fd_reg);
+
+  void DecodeTypeRegisterWRsType(Instruction* instr, const int32_t& fs_reg,
+                                 const int32_t& fd_reg, int64_t& alu_out);
+
+  void DecodeTypeRegisterLRsType(Instruction* instr, const int32_t& fs_reg,
+                                 const int32_t& fd_reg, const int32_t& ft_reg);
   // Executing is handled based on the instruction type.
   void DecodeTypeRegister(Instruction* instr);
 
   // Helper function for DecodeTypeRegister.
   void ConfigureTypeRegister(Instruction* instr,
                              int64_t* alu_out,
                              int64_t* i64hilo,
                              uint64_t* u64hilo,
                              int64_t* next_pc,
                              int64_t* return_addr_reg,
@@ skipping 148 matching lines @@
 
   static inline void UnregisterCTryCatch() {
     Simulator::current(Isolate::Current())->PopAddress();
   }
 };
 
 } }  // namespace v8::internal
 
 #endif  // !defined(USE_SIMULATOR)
 #endif  // V8_MIPS_SIMULATOR_MIPS_H_