MIPS64: [turbofan] Add backend support for float32 operations.

src/mips64/macro-assembler-mips64.h

Index: src/mips64/macro-assembler-mips64.h
diff --git a/src/mips64/macro-assembler-mips64.h b/src/mips64/macro-assembler-mips64.h
index 6088b6164e5d22fa348334a04a9d2c70e80c827e..887b81dc57062a5f091b18cf6e3e354c5cc4dc57 100644
--- a/src/mips64/macro-assembler-mips64.h
+++ b/src/mips64/macro-assembler-mips64.h
@@ -801,7 +801,11 @@ class MacroAssembler: public Assembler {
               FPURegister ft,
               FPURegister scratch);
 
-  // Wrapper function for the different cmp/branch types.
+  // Wrapper functions for the different cmp/branch types.
+  void BranchFSize(SecondaryField sizeField, Label* target, Label* nan,
+                   Condition cc, FPURegister cmp1, FPURegister cmp2,
+                   BranchDelaySlot bd = PROTECT);
+
   void BranchF(Label* target,
                Label* nan,
                Condition cc,
@@ -809,6 +813,9 @@ class MacroAssembler: public Assembler {
                FPURegister cmp2,
                BranchDelaySlot bd = PROTECT);
 
+  void BranchFS(Label* target, Label* nan, Condition cc, FPURegister cmp1,
+                FPURegister cmp2, BranchDelaySlot bd = PROTECT);
+
   // Alternate (inline) version for better readability with USE_DELAY_SLOT.
   inline void BranchF(BranchDelaySlot bd,
                       Label* target,
@@ -819,6 +826,11 @@ class MacroAssembler: public Assembler {
     BranchF(target, nan, cc, cmp1, cmp2, bd);
   }
 
+  inline void BranchFS(BranchDelaySlot bd, Label* target, Label* nan,
+                       Condition cc, FPURegister cmp1, FPURegister cmp2) {
+    BranchFS(target, nan, cc, cmp1, cmp2, bd);
+  }
+
   // Truncates a double using a specific rounding mode, and writes the value
   // to the result register.
   // The except_flag will contain any exceptions caused by the instruction.