MIPS64: [turbofan] Add backend support for float32 operations.

src/mips64/macro-assembler-mips64.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>  // For LONG_MIN, LONG_MAX.
 
 #include "src/v8.h"
 
 #if V8_TARGET_ARCH_MIPS64
 
@@ skipping 1611 matching lines @@
     madd_d(fd, fr, fs, ft);
   } else {
     // Can not change source regs's value.
     DCHECK(!fr.is(scratch) && !fs.is(scratch) && !ft.is(scratch));
     mul_d(scratch, fs, ft);
     add_d(fd, fr, scratch);
   }
 }
 
 
-void MacroAssembler::BranchF(Label* target,
-                             Label* nan,
-                             Condition cc,
-                             FPURegister cmp1,
-                             FPURegister cmp2,
-                             BranchDelaySlot bd) {
+void MacroAssembler::BranchFSize(SecondaryField sizeField, Label* target,
+                                 Label* nan, Condition cc, FPURegister cmp1,
+                                 FPURegister cmp2, BranchDelaySlot bd) {
   BlockTrampolinePoolScope block_trampoline_pool(this);
   if (cc == al) {
     Branch(bd, target);
     return;
   }
 
+  if (kArchVariant == kMips64r6) {
+    sizeField = sizeField == D ? L : W;
+  }
   DCHECK(nan || target);
   // Check for unordered (NaN) cases.
   if (nan) {
     if (kArchVariant != kMips64r6) {
       c(UN, D, cmp1, cmp2);
       bc1t(nan);
     } else {
       // Use f31 for comparison result. It has to be unavailable to lithium
       // register allocator.
       DCHECK(!cmp1.is(f31) && !cmp2.is(f31));
       cmp(UN, L, f31, cmp1, cmp2);
       bc1nez(nan, f31);
     }
   }
 
   if (kArchVariant != kMips64r6) {
     if (target) {
       // Here NaN cases were either handled by this function or are assumed to
       // have been handled by the caller.
       switch (cc) {
         case lt:
-          c(OLT, D, cmp1, cmp2);
+          c(OLT, sizeField, cmp1, cmp2);
           bc1t(target);
           break;
         case gt:
-          c(ULE, D, cmp1, cmp2);
+          c(ULE, sizeField, cmp1, cmp2);
           bc1f(target);
           break;
         case ge:
-          c(ULT, D, cmp1, cmp2);
+          c(ULT, sizeField, cmp1, cmp2);
           bc1f(target);
           break;
         case le:
-          c(OLE, D, cmp1, cmp2);
+          c(OLE, sizeField, cmp1, cmp2);
           bc1t(target);
           break;
         case eq:
-          c(EQ, D, cmp1, cmp2);
+          c(EQ, sizeField, cmp1, cmp2);
           bc1t(target);
           break;
         case ueq:
-          c(UEQ, D, cmp1, cmp2);
+          c(UEQ, sizeField, cmp1, cmp2);
           bc1t(target);
           break;
         case ne:
-          c(EQ, D, cmp1, cmp2);
+          c(EQ, sizeField, cmp1, cmp2);
           bc1f(target);
           break;
         case nue:
-          c(UEQ, D, cmp1, cmp2);
+          c(UEQ, sizeField, cmp1, cmp2);
           bc1f(target);
           break;
         default:
           CHECK(0);
       }
     }
   } else {
     if (target) {
       // Here NaN cases were either handled by this function or are assumed to
       // have been handled by the caller.
       // Unsigned conditions are treated as their signed counterpart.
       // Use f31 for comparison result, it is valid in fp64 (FR = 1) mode.
       DCHECK(!cmp1.is(f31) && !cmp2.is(f31));
       switch (cc) {
         case lt:
-          cmp(OLT, L, f31, cmp1, cmp2);
+          cmp(OLT, sizeField, f31, cmp1, cmp2);
           bc1nez(target, f31);
           break;
         case gt:
-          cmp(ULE, L, f31, cmp1, cmp2);
+          cmp(ULE, sizeField, f31, cmp1, cmp2);
           bc1eqz(target, f31);
           break;
         case ge:
-          cmp(ULT, L, f31, cmp1, cmp2);
+          cmp(ULT, sizeField, f31, cmp1, cmp2);
           bc1eqz(target, f31);
           break;
         case le:
-          cmp(OLE, L, f31, cmp1, cmp2);
+          cmp(OLE, sizeField, f31, cmp1, cmp2);
           bc1nez(target, f31);
           break;
         case eq:
-          cmp(EQ, L, f31, cmp1, cmp2);
+          cmp(EQ, sizeField, f31, cmp1, cmp2);
           bc1nez(target, f31);
           break;
         case ueq:
-          cmp(UEQ, L, f31, cmp1, cmp2);
+          cmp(UEQ, sizeField, f31, cmp1, cmp2);
           bc1nez(target, f31);
           break;
         case ne:
-          cmp(EQ, L, f31, cmp1, cmp2);
+          cmp(EQ, sizeField, f31, cmp1, cmp2);
           bc1eqz(target, f31);
           break;
         case nue:
-          cmp(UEQ, L, f31, cmp1, cmp2);
+          cmp(UEQ, sizeField, f31, cmp1, cmp2);
           bc1eqz(target, f31);
           break;
         default:
           CHECK(0);
       }
     }
   }
 
   if (bd == PROTECT) {
     nop();
   }
 }
 
 
+void MacroAssembler::BranchF(Label* target, Label* nan, Condition cc,
+                             FPURegister cmp1, FPURegister cmp2,
+                             BranchDelaySlot bd) {
+  BranchFSize(D, target, nan, cc, cmp1, cmp2, bd);
+}
+
+
+void MacroAssembler::BranchFS(Label* target, Label* nan, Condition cc,
+                              FPURegister cmp1, FPURegister cmp2,
+                              BranchDelaySlot bd) {
+  BranchFSize(S, target, nan, cc, cmp1, cmp2, bd);
+}
+
+
 void MacroAssembler::FmoveLow(FPURegister dst, Register src_low) {
   DCHECK(!src_low.is(at));
   mfhc1(at, dst);
   mtc1(src_low, dst);
   mthc1(at, dst);
 }
 
 
 void MacroAssembler::Move(FPURegister dst, float imm) {
   li(at, Operand(bit_cast<int32_t>(imm)));
@@ skipping 4368 matching lines @@
   }
   if (mag.shift > 0) sra(result, result, mag.shift);
   srl(at, dividend, 31);
   Addu(result, result, Operand(at));
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_MIPS64