MIPS64: [turbofan] Add backend support for float32 operations.

src/compiler/mips64/instruction-codes-mips64.h

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
 
 namespace v8 {
 namespace internal {
 namespace compiler {
@@ skipping 27 matching lines @@
   V(Mips64Ext)                      \
   V(Mips64Dext)                     \
   V(Mips64Dshl)                     \
   V(Mips64Dshr)                     \
   V(Mips64Dsar)                     \
   V(Mips64Ror)                      \
   V(Mips64Dror)                     \
   V(Mips64Mov)                      \
   V(Mips64Tst)                      \
   V(Mips64Cmp)                      \
+  V(Mips64CmpS)                     \
+  V(Mips64AddS)                     \
+  V(Mips64SubS)                     \
+  V(Mips64MulS)                     \
+  V(Mips64DivS)                     \
+  V(Mips64ModS)                     \
+  V(Mips64SqrtS)                    \
   V(Mips64CmpD)                     \
   V(Mips64AddD)                     \
   V(Mips64SubD)                     \
   V(Mips64MulD)                     \
   V(Mips64DivD)                     \
   V(Mips64ModD)                     \
   V(Mips64SqrtD)                    \
   V(Mips64Float64RoundDown)         \
   V(Mips64Float64RoundTruncate)     \
   V(Mips64Float64RoundUp)           \
@@ skipping 44 matching lines @@
 #define TARGET_ADDRESSING_MODE_LIST(V) \
   V(MRI) /* [%r0 + K] */               \
   V(MRR) /* [%r0 + %r1] */
 
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_