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Side by Side Diff: src/compiler/x64/instruction-codes-x64.h

Issue 1044793002: [turbofan] Add backend support for float32 operations. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Add MachineOperator unit tests. Created 5 years, 8 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_ 5 #ifndef V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_
6 #define V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_ 6 #define V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 29 matching lines...) Expand all
40 V(X64Neg32) \ 40 V(X64Neg32) \
41 V(X64Shl) \ 41 V(X64Shl) \
42 V(X64Shl32) \ 42 V(X64Shl32) \
43 V(X64Shr) \ 43 V(X64Shr) \
44 V(X64Shr32) \ 44 V(X64Shr32) \
45 V(X64Sar) \ 45 V(X64Sar) \
46 V(X64Sar32) \ 46 V(X64Sar32) \
47 V(X64Ror) \ 47 V(X64Ror) \
48 V(X64Ror32) \ 48 V(X64Ror32) \
49 V(X64Lzcnt32) \ 49 V(X64Lzcnt32) \
50 V(SSEFloat32Cmp) \
51 V(SSEFloat32Add) \
52 V(SSEFloat32Sub) \
53 V(SSEFloat32Mul) \
54 V(SSEFloat32Div) \
55 V(SSEFloat32Sqrt) \
56 V(SSEFloat32Max) \
57 V(SSEFloat32Min) \
58 V(SSEFloat32ToFloat64) \
50 V(SSEFloat64Cmp) \ 59 V(SSEFloat64Cmp) \
51 V(SSEFloat64Add) \ 60 V(SSEFloat64Add) \
52 V(SSEFloat64Sub) \ 61 V(SSEFloat64Sub) \
53 V(SSEFloat64Mul) \ 62 V(SSEFloat64Mul) \
54 V(SSEFloat64Div) \ 63 V(SSEFloat64Div) \
55 V(SSEFloat64Mod) \ 64 V(SSEFloat64Mod) \
56 V(SSEFloat64Sqrt) \ 65 V(SSEFloat64Sqrt) \
57 V(SSEFloat64Round) \ 66 V(SSEFloat64Round) \
58 V(SSEFloat64Max) \ 67 V(SSEFloat64Max) \
59 V(SSEFloat64Min) \ 68 V(SSEFloat64Min) \
60 V(SSECvtss2sd) \ 69 V(SSEFloat64ToFloat32) \
61 V(SSECvtsd2ss) \
62 V(SSEFloat64ToInt32) \ 70 V(SSEFloat64ToInt32) \
63 V(SSEFloat64ToUint32) \ 71 V(SSEFloat64ToUint32) \
64 V(SSEInt32ToFloat64) \ 72 V(SSEInt32ToFloat64) \
65 V(SSEUint32ToFloat64) \ 73 V(SSEUint32ToFloat64) \
66 V(SSEFloat64ExtractLowWord32) \ 74 V(SSEFloat64ExtractLowWord32) \
67 V(SSEFloat64ExtractHighWord32) \ 75 V(SSEFloat64ExtractHighWord32) \
68 V(SSEFloat64InsertLowWord32) \ 76 V(SSEFloat64InsertLowWord32) \
69 V(SSEFloat64InsertHighWord32) \ 77 V(SSEFloat64InsertHighWord32) \
70 V(SSEFloat64LoadLowWord32) \ 78 V(SSEFloat64LoadLowWord32) \
79 V(AVXFloat32Cmp) \
80 V(AVXFloat32Add) \
81 V(AVXFloat32Sub) \
82 V(AVXFloat32Mul) \
83 V(AVXFloat32Div) \
84 V(AVXFloat32Max) \
85 V(AVXFloat32Min) \
86 V(AVXFloat64Cmp) \
71 V(AVXFloat64Add) \ 87 V(AVXFloat64Add) \
72 V(AVXFloat64Sub) \ 88 V(AVXFloat64Sub) \
73 V(AVXFloat64Mul) \ 89 V(AVXFloat64Mul) \
74 V(AVXFloat64Div) \ 90 V(AVXFloat64Div) \
75 V(AVXFloat64Max) \ 91 V(AVXFloat64Max) \
76 V(AVXFloat64Min) \ 92 V(AVXFloat64Min) \
77 V(X64Movsxbl) \ 93 V(X64Movsxbl) \
78 V(X64Movzxbl) \ 94 V(X64Movzxbl) \
79 V(X64Movb) \ 95 V(X64Movb) \
80 V(X64Movsxwl) \ 96 V(X64Movsxwl) \
(...skipping 43 matching lines...) Expand 10 before | Expand all | Expand 10 after
124 V(M1I) /* [ %r2*1 + K] */ \ 140 V(M1I) /* [ %r2*1 + K] */ \
125 V(M2I) /* [ %r2*2 + K] */ \ 141 V(M2I) /* [ %r2*2 + K] */ \
126 V(M4I) /* [ %r2*4 + K] */ \ 142 V(M4I) /* [ %r2*4 + K] */ \
127 V(M8I) /* [ %r2*8 + K] */ 143 V(M8I) /* [ %r2*8 + K] */
128 144
129 } // namespace compiler 145 } // namespace compiler
130 } // namespace internal 146 } // namespace internal
131 } // namespace v8 147 } // namespace v8
132 148
133 #endif // V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_ 149 #endif // V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_
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