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Side by Side Diff: src/compiler/ia32/instruction-codes-ia32.h

Issue 1044793002: [turbofan] Add backend support for float32 operations. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Add MachineOperator unit tests. Created 5 years, 8 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ 5 #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
6 #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ 6 #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 13 matching lines...) Expand all
24 V(IA32UmulHigh) \ 24 V(IA32UmulHigh) \
25 V(IA32Idiv) \ 25 V(IA32Idiv) \
26 V(IA32Udiv) \ 26 V(IA32Udiv) \
27 V(IA32Not) \ 27 V(IA32Not) \
28 V(IA32Neg) \ 28 V(IA32Neg) \
29 V(IA32Shl) \ 29 V(IA32Shl) \
30 V(IA32Shr) \ 30 V(IA32Shr) \
31 V(IA32Sar) \ 31 V(IA32Sar) \
32 V(IA32Ror) \ 32 V(IA32Ror) \
33 V(IA32Lzcnt) \ 33 V(IA32Lzcnt) \
34 V(SSEFloat32Cmp) \
35 V(SSEFloat32Add) \
36 V(SSEFloat32Sub) \
37 V(SSEFloat32Mul) \
38 V(SSEFloat32Div) \
39 V(SSEFloat32Max) \
40 V(SSEFloat32Min) \
41 V(SSEFloat32Sqrt) \
34 V(SSEFloat64Cmp) \ 42 V(SSEFloat64Cmp) \
35 V(SSEFloat64Add) \ 43 V(SSEFloat64Add) \
36 V(SSEFloat64Sub) \ 44 V(SSEFloat64Sub) \
37 V(SSEFloat64Mul) \ 45 V(SSEFloat64Mul) \
38 V(SSEFloat64Div) \ 46 V(SSEFloat64Div) \
39 V(SSEFloat64Mod) \ 47 V(SSEFloat64Mod) \
40 V(SSEFloat64Max) \ 48 V(SSEFloat64Max) \
41 V(SSEFloat64Min) \ 49 V(SSEFloat64Min) \
42 V(SSEFloat64Sqrt) \ 50 V(SSEFloat64Sqrt) \
43 V(SSEFloat64Round) \ 51 V(SSEFloat64Round) \
44 V(SSECvtss2sd) \ 52 V(SSEFloat32ToFloat64) \
45 V(SSECvtsd2ss) \ 53 V(SSEFloat64ToFloat32) \
46 V(SSEFloat64ToInt32) \ 54 V(SSEFloat64ToInt32) \
47 V(SSEFloat64ToUint32) \ 55 V(SSEFloat64ToUint32) \
48 V(SSEInt32ToFloat64) \ 56 V(SSEInt32ToFloat64) \
49 V(SSEUint32ToFloat64) \ 57 V(SSEUint32ToFloat64) \
50 V(SSEFloat64ExtractLowWord32) \ 58 V(SSEFloat64ExtractLowWord32) \
51 V(SSEFloat64ExtractHighWord32) \ 59 V(SSEFloat64ExtractHighWord32) \
52 V(SSEFloat64InsertLowWord32) \ 60 V(SSEFloat64InsertLowWord32) \
53 V(SSEFloat64InsertHighWord32) \ 61 V(SSEFloat64InsertHighWord32) \
54 V(SSEFloat64LoadLowWord32) \ 62 V(SSEFloat64LoadLowWord32) \
63 V(AVXFloat32Add) \
64 V(AVXFloat32Sub) \
65 V(AVXFloat32Mul) \
66 V(AVXFloat32Div) \
67 V(AVXFloat32Max) \
68 V(AVXFloat32Min) \
55 V(AVXFloat64Add) \ 69 V(AVXFloat64Add) \
56 V(AVXFloat64Sub) \ 70 V(AVXFloat64Sub) \
57 V(AVXFloat64Mul) \ 71 V(AVXFloat64Mul) \
58 V(AVXFloat64Div) \ 72 V(AVXFloat64Div) \
59 V(AVXFloat64Max) \ 73 V(AVXFloat64Max) \
60 V(AVXFloat64Min) \ 74 V(AVXFloat64Min) \
61 V(IA32Movsxbl) \ 75 V(IA32Movsxbl) \
62 V(IA32Movzxbl) \ 76 V(IA32Movzxbl) \
63 V(IA32Movb) \ 77 V(IA32Movb) \
64 V(IA32Movsxwl) \ 78 V(IA32Movsxwl) \
(...skipping 39 matching lines...) Expand 10 before | Expand all | Expand 10 after
104 V(M2I) /* [ %r2*2 + K] */ \ 118 V(M2I) /* [ %r2*2 + K] */ \
105 V(M4I) /* [ %r2*4 + K] */ \ 119 V(M4I) /* [ %r2*4 + K] */ \
106 V(M8I) /* [ %r2*8 + K] */ \ 120 V(M8I) /* [ %r2*8 + K] */ \
107 V(MI) /* [ K] */ 121 V(MI) /* [ K] */
108 122
109 } // namespace compiler 123 } // namespace compiler
110 } // namespace internal 124 } // namespace internal
111 } // namespace v8 125 } // namespace v8
112 126
113 #endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ 127 #endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
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