Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(481)

Issues Search
    My Issues | Starred     Open | Closed | All

Side by Side Diff: src/compiler/arm64/instruction-codes-arm64.h

Issue 1044793002: [turbofan] Add backend support for float32 operations. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Add MachineOperator unit tests. Created 5 years, 8 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « src/compiler/arm64/code-generator-arm64.cc ('k') | src/compiler/arm64/instruction-selector-arm64.cc » ('j') | test/cctest/test-disasm-arm.cc » ('J')
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 60 matching lines...) Expand 10 before | Expand all | Expand 10 after
71 V(Arm64Sxtw) \ 71 V(Arm64Sxtw) \
72 V(Arm64Ubfx) \ 72 V(Arm64Ubfx) \
73 V(Arm64Ubfx32) \ 73 V(Arm64Ubfx32) \
74 V(Arm64Bfi) \ 74 V(Arm64Bfi) \
75 V(Arm64TestAndBranch32) \ 75 V(Arm64TestAndBranch32) \
76 V(Arm64TestAndBranch) \ 76 V(Arm64TestAndBranch) \
77 V(Arm64CompareAndBranch32) \ 77 V(Arm64CompareAndBranch32) \
78 V(Arm64Claim) \ 78 V(Arm64Claim) \
79 V(Arm64Poke) \ 79 V(Arm64Poke) \
80 V(Arm64PokePair) \ 80 V(Arm64PokePair) \
81 V(Arm64Float32Cmp) \
82 V(Arm64Float32Add) \
83 V(Arm64Float32Sub) \
84 V(Arm64Float32Mul) \
85 V(Arm64Float32Div) \
86 V(Arm64Float32Max) \
87 V(Arm64Float32Min) \
88 V(Arm64Float32Sqrt) \
81 V(Arm64Float64Cmp) \ 89 V(Arm64Float64Cmp) \
82 V(Arm64Float64Add) \ 90 V(Arm64Float64Add) \
83 V(Arm64Float64Sub) \ 91 V(Arm64Float64Sub) \
84 V(Arm64Float64Mul) \ 92 V(Arm64Float64Mul) \
85 V(Arm64Float64Div) \ 93 V(Arm64Float64Div) \
86 V(Arm64Float64Mod) \ 94 V(Arm64Float64Mod) \
95 V(Arm64Float64Max) \
96 V(Arm64Float64Min) \
87 V(Arm64Float64Sqrt) \ 97 V(Arm64Float64Sqrt) \
88 V(Arm64Float64RoundDown) \ 98 V(Arm64Float64RoundDown) \
89 V(Arm64Float64RoundTiesAway) \ 99 V(Arm64Float64RoundTiesAway) \
90 V(Arm64Float64RoundTruncate) \ 100 V(Arm64Float64RoundTruncate) \
91 V(Arm64Float64RoundUp) \ 101 V(Arm64Float64RoundUp) \
92 V(Arm64Float32ToFloat64) \ 102 V(Arm64Float32ToFloat64) \
93 V(Arm64Float64ToFloat32) \ 103 V(Arm64Float64ToFloat32) \
94 V(Arm64Float64ToInt32) \ 104 V(Arm64Float64ToInt32) \
95 V(Arm64Float64ToUint32) \ 105 V(Arm64Float64ToUint32) \
96 V(Arm64Int32ToFloat64) \ 106 V(Arm64Int32ToFloat64) \
97 V(Arm64Uint32ToFloat64) \ 107 V(Arm64Uint32ToFloat64) \
98 V(Arm64Float64ExtractLowWord32) \ 108 V(Arm64Float64ExtractLowWord32) \
99 V(Arm64Float64ExtractHighWord32) \ 109 V(Arm64Float64ExtractHighWord32) \
100 V(Arm64Float64InsertLowWord32) \ 110 V(Arm64Float64InsertLowWord32) \
101 V(Arm64Float64InsertHighWord32) \ 111 V(Arm64Float64InsertHighWord32) \
102 V(Arm64Float64MoveU64) \ 112 V(Arm64Float64MoveU64) \
103 V(Arm64Float64Max) \
104 V(Arm64Float64Min) \
105 V(Arm64LdrS) \ 113 V(Arm64LdrS) \
106 V(Arm64StrS) \ 114 V(Arm64StrS) \
107 V(Arm64LdrD) \ 115 V(Arm64LdrD) \
108 V(Arm64StrD) \ 116 V(Arm64StrD) \
109 V(Arm64Ldrb) \ 117 V(Arm64Ldrb) \
110 V(Arm64Ldrsb) \ 118 V(Arm64Ldrsb) \
111 V(Arm64Strb) \ 119 V(Arm64Strb) \
112 V(Arm64Ldrh) \ 120 V(Arm64Ldrh) \
113 V(Arm64Ldrsh) \ 121 V(Arm64Ldrsh) \
114 V(Arm64Strh) \ 122 V(Arm64Strh) \
(...skipping 25 matching lines...) Expand all
140 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ 148 V(Operand2_R_ASR_I) /* %r0 ASR K */ \
141 V(Operand2_R_ROR_I) /* %r0 ROR K */ \ 149 V(Operand2_R_ROR_I) /* %r0 ROR K */ \
142 V(Operand2_R_UXTB) /* %r0 UXTB (unsigned extend byte) */ \ 150 V(Operand2_R_UXTB) /* %r0 UXTB (unsigned extend byte) */ \
143 V(Operand2_R_UXTH) /* %r0 UXTH (unsigned extend halfword) */ 151 V(Operand2_R_UXTH) /* %r0 UXTH (unsigned extend halfword) */
144 152
145 } // namespace internal 153 } // namespace internal
146 } // namespace compiler 154 } // namespace compiler
147 } // namespace v8 155 } // namespace v8
148 156
149 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 157 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
OLDNEW
« no previous file with comments | « src/compiler/arm64/code-generator-arm64.cc ('k') | src/compiler/arm64/instruction-selector-arm64.cc » ('j') | test/cctest/test-disasm-arm.cc » ('J')

Powered by Google App Engine
This is Rietveld 408576698