[turbofan] Add backend support for float32 operations.

src/arm/simulator-arm.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <stdarg.h>
 #include <stdlib.h>
 #include <cmath>
 
 #include "src/v8.h"
 
@@ skipping 1291 matching lines @@
                // operands have different signs
     overflow = ((left < 0 && right >= 0) || (left >= 0 && right < 0))
                // and first operand and result have different signs
                && ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0));
   }
   return overflow;
 }
 
 
 // Support for VFP comparisons.
+void Simulator::Compute_FPSCR_Flags(float val1, float val2) {
+  if (std::isnan(val1) || std::isnan(val2)) {
+    n_flag_FPSCR_ = false;
+    z_flag_FPSCR_ = false;
+    c_flag_FPSCR_ = true;
+    v_flag_FPSCR_ = true;
+    // All non-NaN cases.
+  } else if (val1 == val2) {
+    n_flag_FPSCR_ = false;
+    z_flag_FPSCR_ = true;
+    c_flag_FPSCR_ = true;
+    v_flag_FPSCR_ = false;
+  } else if (val1 < val2) {
+    n_flag_FPSCR_ = true;
+    z_flag_FPSCR_ = false;
+    c_flag_FPSCR_ = false;
+    v_flag_FPSCR_ = false;
+  } else {
+    // Case when (val1 > val2).
+    n_flag_FPSCR_ = false;
+    z_flag_FPSCR_ = false;
+    c_flag_FPSCR_ = true;
+    v_flag_FPSCR_ = false;
+  }
+}
+
+
 void Simulator::Compute_FPSCR_Flags(double val1, double val2) {
   if (std::isnan(val1) || std::isnan(val2)) {
     n_flag_FPSCR_ = false;
     z_flag_FPSCR_ = false;
     c_flag_FPSCR_ = true;
     v_flag_FPSCR_ = true;
   // All non-NaN cases.
   } else if (val1 == val2) {
     n_flag_FPSCR_ = false;
     z_flag_FPSCR_ = true;
@@ skipping 585 matching lines @@
       } else {
         // This is not a valid svc code.
         UNREACHABLE();
         break;
       }
     }
   }
 }
 
 
+float Simulator::canonicalizeNaN(float value) {
+  // Default NaN value, see "NaN handling" in "IEEE 754 standard implementation
+  // choices" of the ARM Reference Manual.
+  const uint32_t kDefaultNaN = 0x7FC00000u;
+  if (FPSCR_default_NaN_mode_ && std::isnan(value)) {
+    value = bit_cast<float>(kDefaultNaN);
+  }
+  return value;
+}
+
+
 double Simulator::canonicalizeNaN(double value) {
   // Default NaN value, see "NaN handling" in "IEEE 754 standard implementation
   // choices" of the ARM Reference Manual.
   const uint64_t kDefaultNaN = V8_UINT64_C(0x7FF8000000000000);
   if (FPSCR_default_NaN_mode_ && std::isnan(value)) {
     value = bit_cast<double>(kDefaultNaN);
   }
   return value;
 }
 
@@ skipping 1075 matching lines @@
 
 
 // void Simulator::DecodeTypeVFP(Instruction* instr)
 // The Following ARMv7 VFPv instructions are currently supported.
 // vmov :Sn = Rt
 // vmov :Rt = Sn
 // vcvt: Dd = Sm
 // vcvt: Sd = Dm
 // vcvt.f64.s32 Dd, Dd, #<fbits>
 // Dd = vabs(Dm)
+// Sd = vabs(Sm)
 // Dd = vneg(Dm)
+// Sd = vneg(Sm)
 // Dd = vadd(Dn, Dm)
+// Sd = vadd(Sn, Sm)
 // Dd = vsub(Dn, Dm)
+// Sd = vsub(Sn, Sm)
 // Dd = vmul(Dn, Dm)
+// Sd = vmul(Sn, Sm)
 // Dd = vdiv(Dn, Dm)
+// Sd = vdiv(Sn, Sm)
 // vcmp(Dd, Dm)
+// vcmp(Sd, Sm)
+// Dd = vsqrt(Dm)
+// Sd = vsqrt(Sm)
 // vmrs
-// Dd = vsqrt(Dm)
 void Simulator::DecodeTypeVFP(Instruction* instr) {
   DCHECK((instr->TypeValue() == 7) && (instr->Bit(24) == 0x0) );
   DCHECK(instr->Bits(11, 9) == 0x5);
 
+  // Obtain single precision register codes.
+  int m = instr->VFPMRegValue(kSinglePrecision);
+  int d = instr->VFPDRegValue(kSinglePrecision);
+  int n = instr->VFPNRegValue(kSinglePrecision);
   // Obtain double precision register codes.
   int vm = instr->VFPMRegValue(kDoublePrecision);
   int vd = instr->VFPDRegValue(kDoublePrecision);
   int vn = instr->VFPNRegValue(kDoublePrecision);
 
   if (instr->Bit(4) == 0) {
     if (instr->Opc1Value() == 0x7) {
       // Other data processing instructions
       if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x1)) {
         // vmov register to register.
         if (instr->SzValue() == 0x1) {
-          int m = instr->VFPMRegValue(kDoublePrecision);
-          int d = instr->VFPDRegValue(kDoublePrecision);
           uint32_t data[2];
-          get_d_register(m, data);
-          set_d_register(d, data);
+          get_d_register(vm, data);
+          set_d_register(vd, data);
         } else {
-          int m = instr->VFPMRegValue(kSinglePrecision);
-          int d = instr->VFPDRegValue(kSinglePrecision);
-          set_s_register_from_float(d, get_float_from_s_register(m));
+          set_s_register(d, get_s_register(m));
         }
       } else if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x3)) {
         // vabs
-        double dm_value = get_double_from_d_register(vm);
-        double dd_value = std::fabs(dm_value);
-        dd_value = canonicalizeNaN(dd_value);
-        set_d_register_from_double(vd, dd_value);
+        if (instr->SzValue() == 0x1) {
+          double dm_value = get_double_from_d_register(vm);
+          double dd_value = std::fabs(dm_value);
+          dd_value = canonicalizeNaN(dd_value);
+          set_d_register_from_double(vd, dd_value);
+        } else {
+          float sm_value = get_float_from_s_register(m);
+          float sd_value = std::fabs(sm_value);
+          sd_value = canonicalizeNaN(sd_value);
+          set_s_register_from_float(d, sd_value);
+        }
       } else if ((instr->Opc2Value() == 0x1) && (instr->Opc3Value() == 0x1)) {
         // vneg
-        double dm_value = get_double_from_d_register(vm);
-        double dd_value = -dm_value;
-        dd_value = canonicalizeNaN(dd_value);
-        set_d_register_from_double(vd, dd_value);
+        if (instr->SzValue() == 0x1) {
+          double dm_value = get_double_from_d_register(vm);
+          double dd_value = -dm_value;
+          dd_value = canonicalizeNaN(dd_value);
+          set_d_register_from_double(vd, dd_value);
+        } else {
+          float sm_value = get_float_from_s_register(m);
+          float sd_value = -sm_value;
+          sd_value = canonicalizeNaN(sd_value);
+          set_s_register_from_float(d, sd_value);
+        }
       } else if ((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3)) {
         DecodeVCVTBetweenDoubleAndSingle(instr);
       } else if ((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) {
         DecodeVCVTBetweenFloatingPointAndInteger(instr);
       } else if ((instr->Opc2Value() == 0xA) && (instr->Opc3Value() == 0x3) &&
                  (instr->Bit(8) == 1)) {
         // vcvt.f64.s32 Dd, Dd, #<fbits>
         int fraction_bits = 32 - ((instr->Bits(3, 0) << 1) | instr->Bit(5));
         int fixed_value = get_sinteger_from_s_register(vd * 2);
         double divide = 1 << fraction_bits;
         set_d_register_from_double(vd, fixed_value / divide);
       } else if (((instr->Opc2Value() >> 1) == 0x6) &&
                  (instr->Opc3Value() & 0x1)) {
         DecodeVCVTBetweenFloatingPointAndInteger(instr);
       } else if (((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
                  (instr->Opc3Value() & 0x1)) {
         DecodeVCMP(instr);
       } else if (((instr->Opc2Value() == 0x1)) && (instr->Opc3Value() == 0x3)) {
         // vsqrt
-        double dm_value = get_double_from_d_register(vm);
-        double dd_value = fast_sqrt(dm_value);
-        dd_value = canonicalizeNaN(dd_value);
-        set_d_register_from_double(vd, dd_value);
+        if (instr->SzValue() == 0x1) {
+          double dm_value = get_double_from_d_register(vm);
+          double dd_value = fast_sqrt(dm_value);
+          dd_value = canonicalizeNaN(dd_value);
+          set_d_register_from_double(vd, dd_value);
+        } else {
+          float sm_value = get_float_from_s_register(m);
+          float sd_value = fast_sqrt(sm_value);
+          sd_value = canonicalizeNaN(sd_value);
+          set_s_register_from_float(d, sd_value);
+        }
       } else if (instr->Opc3Value() == 0x0) {
         // vmov immediate.
         if (instr->SzValue() == 0x1) {
           set_d_register_from_double(vd, instr->DoubleImmedVmov());
         } else {
           UNREACHABLE();  // Not used by v8.
         }
       } else if (((instr->Opc2Value() == 0x6)) && (instr->Opc3Value() == 0x3)) {
         // vrintz - truncate
         double dm_value = get_double_from_d_register(vm);
         double dd_value = trunc(dm_value);
         dd_value = canonicalizeNaN(dd_value);
         set_d_register_from_double(vd, dd_value);
       } else {
         UNREACHABLE();  // Not used by V8.
       }
     } else if (instr->Opc1Value() == 0x3) {
-      if (instr->SzValue() != 0x1) {
-        UNREACHABLE();  // Not used by V8.
-      }
-
       if (instr->Opc3Value() & 0x1) {
         // vsub
+        if (instr->SzValue() == 0x1) {
+          double dn_value = get_double_from_d_register(vn);
+          double dm_value = get_double_from_d_register(vm);
+          double dd_value = dn_value - dm_value;
+          dd_value = canonicalizeNaN(dd_value);
+          set_d_register_from_double(vd, dd_value);
+        } else {
+          float sn_value = get_float_from_s_register(n);
+          float sm_value = get_float_from_s_register(m);
+          float sd_value = sn_value - sm_value;
+          sd_value = canonicalizeNaN(sd_value);
+          set_s_register_from_float(d, sd_value);
+        }
+      } else {
+        // vadd
+        if (instr->SzValue() == 0x1) {
+          double dn_value = get_double_from_d_register(vn);
+          double dm_value = get_double_from_d_register(vm);
+          double dd_value = dn_value + dm_value;
+          dd_value = canonicalizeNaN(dd_value);
+          set_d_register_from_double(vd, dd_value);
+        } else {
+          float sn_value = get_float_from_s_register(n);
+          float sm_value = get_float_from_s_register(m);
+          float sd_value = sn_value + sm_value;
+          sd_value = canonicalizeNaN(sd_value);
+          set_s_register_from_float(d, sd_value);
+        }
+      }
+    } else if ((instr->Opc1Value() == 0x2) && !(instr->Opc3Value() & 0x1)) {
+      // vmul
+      if (instr->SzValue() == 0x1) {
         double dn_value = get_double_from_d_register(vn);
         double dm_value = get_double_from_d_register(vm);
-        double dd_value = dn_value - dm_value;
+        double dd_value = dn_value * dm_value;
         dd_value = canonicalizeNaN(dd_value);
         set_d_register_from_double(vd, dd_value);
       } else {
-        // vadd
-        double dn_value = get_double_from_d_register(vn);
-        double dm_value = get_double_from_d_register(vm);
-        double dd_value = dn_value + dm_value;
-        dd_value = canonicalizeNaN(dd_value);
-        set_d_register_from_double(vd, dd_value);
+        float sn_value = get_float_from_s_register(n);
+        float sm_value = get_float_from_s_register(m);
+        float sd_value = sn_value * sm_value;
+        sd_value = canonicalizeNaN(sd_value);
+        set_s_register_from_float(d, sd_value);
       }
-    } else if ((instr->Opc1Value() == 0x2) && !(instr->Opc3Value() & 0x1)) {
-      // vmul
-      if (instr->SzValue() != 0x1) {
-        UNREACHABLE();  // Not used by V8.
-      }
-
-      double dn_value = get_double_from_d_register(vn);
-      double dm_value = get_double_from_d_register(vm);
-      double dd_value = dn_value * dm_value;
-      dd_value = canonicalizeNaN(dd_value);
-      set_d_register_from_double(vd, dd_value);
     } else if ((instr->Opc1Value() == 0x0)) {
       // vmla, vmls
       const bool is_vmls = (instr->Opc3Value() & 0x1);
+      if (instr->SzValue() == 0x1) {
+        const double dd_val = get_double_from_d_register(vd);
+        const double dn_val = get_double_from_d_register(vn);
+        const double dm_val = get_double_from_d_register(vm);
 
-      if (instr->SzValue() != 0x1) {
-        UNREACHABLE();  // Not used by V8.
-      }
+        // Note: we do the mul and add/sub in separate steps to avoid getting a
+        // result with too high precision.
+        set_d_register_from_double(vd, dn_val * dm_val);
+        if (is_vmls) {
+          set_d_register_from_double(
+              vd, canonicalizeNaN(dd_val - get_double_from_d_register(vd)));
+        } else {
+          set_d_register_from_double(
+              vd, canonicalizeNaN(dd_val + get_double_from_d_register(vd)));
+        }
+      } else {
+        const float sd_val = get_float_from_s_register(d);
+        const float sn_val = get_float_from_s_register(n);
+        const float sm_val = get_float_from_s_register(m);
 
-      const double dd_val = get_double_from_d_register(vd);
-      const double dn_val = get_double_from_d_register(vn);
-      const double dm_val = get_double_from_d_register(vm);
-
-      // Note: we do the mul and add/sub in separate steps to avoid getting a
-      // result with too high precision.
-      set_d_register_from_double(vd, dn_val * dm_val);
-      if (is_vmls) {
-        set_d_register_from_double(
-          vd,
-          canonicalizeNaN(dd_val - get_double_from_d_register(vd)));
-      } else {
-        set_d_register_from_double(
-          vd,
-          canonicalizeNaN(dd_val + get_double_from_d_register(vd)));
+        // Note: we do the mul and add/sub in separate steps to avoid getting a
+        // result with too high precision.
+        set_s_register_from_float(d, sn_val * sm_val);
+        if (is_vmls) {
+          set_s_register_from_float(
+              d, canonicalizeNaN(sd_val - get_float_from_s_register(d)));
+        } else {
+          set_s_register_from_float(
+              d, canonicalizeNaN(sd_val + get_float_from_s_register(d)));
+        }
       }
     } else if ((instr->Opc1Value() == 0x4) && !(instr->Opc3Value() & 0x1)) {
       // vdiv
-      if (instr->SzValue() != 0x1) {
-        UNREACHABLE();  // Not used by V8.
+      if (instr->SzValue() == 0x1) {
+        double dn_value = get_double_from_d_register(vn);
+        double dm_value = get_double_from_d_register(vm);
+        double dd_value = dn_value / dm_value;
+        div_zero_vfp_flag_ = (dm_value == 0);
+        dd_value = canonicalizeNaN(dd_value);
+        set_d_register_from_double(vd, dd_value);
+      } else {
+        float sn_value = get_float_from_s_register(n);
+        float sm_value = get_float_from_s_register(m);
+        float sd_value = sn_value / sm_value;
+        div_zero_vfp_flag_ = (sm_value == 0);
+        sd_value = canonicalizeNaN(sd_value);
+        set_s_register_from_float(d, sd_value);
       }
-
-      double dn_value = get_double_from_d_register(vn);
-      double dm_value = get_double_from_d_register(vm);
-      double dd_value = dn_value / dm_value;
-      div_zero_vfp_flag_ = (dm_value == 0);
-      dd_value = canonicalizeNaN(dd_value);
-      set_d_register_from_double(vd, dd_value);
     } else {
       UNIMPLEMENTED();  // Not used by V8.
     }
   } else {
     if ((instr->VCValue() == 0x0) &&
         (instr->VAValue() == 0x0)) {
       DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(instr);
     } else if ((instr->VLValue() == 0x0) &&
                (instr->VCValue() == 0x1) &&
                (instr->Bit(23) == 0x0)) {
@@ skipping 84 matching lines @@
 }
 
 
 void Simulator::DecodeVCMP(Instruction* instr) {
   DCHECK((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
   DCHECK(((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
          (instr->Opc3Value() & 0x1));
   // Comparison.
 
   VFPRegPrecision precision = kSinglePrecision;
-  if (instr->SzValue() == 1) {
+  if (instr->SzValue() == 0x1) {
     precision = kDoublePrecision;
   }
 
   int d = instr->VFPDRegValue(precision);
   int m = 0;
   if (instr->Opc2Value() == 0x4) {
     m = instr->VFPMRegValue(precision);
   }
 
   if (precision == kDoublePrecision) {
     double dd_value = get_double_from_d_register(d);
     double dm_value = 0.0;
     if (instr->Opc2Value() == 0x4) {
       dm_value = get_double_from_d_register(m);
     }
 
     // Raise exceptions for quiet NaNs if necessary.
     if (instr->Bit(7) == 1) {
       if (std::isnan(dd_value)) {
         inv_op_vfp_flag_ = true;
       }
     }
 
     Compute_FPSCR_Flags(dd_value, dm_value);
   } else {
-    UNIMPLEMENTED();  // Not used by V8.
+    float sd_value = get_float_from_s_register(d);
+    float sm_value = 0.0;
+    if (instr->Opc2Value() == 0x4) {
+      sm_value = get_float_from_s_register(m);
+    }
+
+    // Raise exceptions for quiet NaNs if necessary.
+    if (instr->Bit(7) == 1) {
+      if (std::isnan(sd_value)) {
+        inv_op_vfp_flag_ = true;
+      }
+    }
+
+    Compute_FPSCR_Flags(sd_value, sm_value);
   }
 }
 
 
 void Simulator::DecodeVCVTBetweenDoubleAndSingle(Instruction* instr) {
   DCHECK((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
   DCHECK((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3));
 
   VFPRegPrecision dst_precision = kDoublePrecision;
   VFPRegPrecision src_precision = kSinglePrecision;
@@ skipping 715 matching lines @@
   uintptr_t address = *stack_slot;
   set_register(sp, current_sp + sizeof(uintptr_t));
   return address;
 }
 
 } }  // namespace v8::internal
 
 #endif  // USE_SIMULATOR
 
 #endif  // V8_TARGET_ARCH_ARM