A few fixes for ARMv5TE.

runtime/vm/intermediate_language_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM.
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/intermediate_language.h"
 
 #include "vm/cpu.h"
@@ skipping 3036 matching lines @@
     if (RightIsPowerOfTwoConstant()) {
       num_temps = 1;
     } else {
       num_temps = 2;
     }
   } else if (op_kind() == Token::kMOD) {
     num_temps = 2;
   } else if (((op_kind() == Token::kSHL) && can_overflow()) ||
              (op_kind() == Token::kSHR)) {
     num_temps = 1;
-  } else if ((op_kind() == Token::kMUL) &&
-             (TargetCPUFeatures::arm_version() != ARMv7)) {
-    num_temps = 1;
   }
   LocationSummary* summary = new(zone) LocationSummary(
       zone, kNumInputs, num_temps, LocationSummary::kNoCall);
   if (op_kind() == Token::kTRUNCDIV) {
     summary->set_in(0, Location::RequiresRegister());
     if (RightIsPowerOfTwoConstant()) {
       ConstantInstr* right_constant = right()->definition()->AsConstant();
       summary->set_in(1, Location::Constant(right_constant));
       summary->set_temp(0, Location::RequiresRegister());
     } else {
@@ skipping 11 matching lines @@
     summary->set_temp(1, Location::RequiresFpuRegister());
     summary->set_out(0, Location::RequiresRegister());
     return summary;
   }
   summary->set_in(0, Location::RequiresRegister());
   summary->set_in(1, Location::RegisterOrSmiConstant(right()));
   if (((op_kind() == Token::kSHL) && can_overflow()) ||
       (op_kind() == Token::kSHR)) {
     summary->set_temp(0, Location::RequiresRegister());
   }
-  if (op_kind() == Token::kMUL) {
-    if (TargetCPUFeatures::arm_version() != ARMv7) {
-      summary->set_temp(0, Location::RequiresFpuRegister());
-    }
-  }
   // We make use of 3-operand instructions by not requiring result register
   // to be identical to first input register as on Intel.
   summary->set_out(0, Location::RequiresRegister());
   return summary;
 }
 
 
 void BinarySmiOpInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   if (op_kind() == Token::kSHL) {
     EmitSmiShiftLeft(compiler, this);
@@ skipping 32 matching lines @@
         }
         break;
       }
       case Token::kMUL: {
         // Keep left value tagged and untag right value.
         const intptr_t value = Smi::Cast(constant).Value();
         if (deopt == NULL) {
           __ LoadImmediate(IP, value);
           __ mul(result, left, IP);
         } else {
-          if (TargetCPUFeatures::arm_version() == ARMv7) {
-            __ LoadImmediate(IP, value);
-            __ smull(result, IP, left, IP);
-            // IP: result bits 32..63.
-            __ cmp(IP, Operand(result, ASR, 31));
-            __ b(deopt, NE);
-          } else if (TargetCPUFeatures::can_divide()) {
-            const QRegister qtmp = locs()->temp(0).fpu_reg();
-            const DRegister dtmp0 = EvenDRegisterOf(qtmp);
-            const DRegister dtmp1 = OddDRegisterOf(qtmp);
-            __ LoadImmediate(IP, value);
-            __ CheckMultSignedOverflow(left, IP, result, dtmp0, dtmp1, deopt);
-            __ mul(result, left, IP);
-          } else {
-           // TODO(vegorov): never emit this instruction if hardware does not
-           // support it! This will lead to deopt cycle penalizing the code.
-            __ b(deopt);
-          }
+          __ LoadImmediate(IP, value);
+          __ smull(result, IP, left, IP);
+          // IP: result bits 32..63.
+          __ cmp(IP, Operand(result, ASR, 31));
+          __ b(deopt, NE);
         }
         break;
       }
       case Token::kTRUNCDIV: {
         const intptr_t value = Smi::Cast(constant).Value();
         ASSERT(Utils::IsPowerOfTwo(Utils::Abs(value)));
         const intptr_t shift_count =
             Utils::ShiftForPowerOfTwo(Utils::Abs(value)) + kSmiTagSize;
         ASSERT(kSmiTagSize == 1);
         __ mov(IP, Operand(left, ASR, 31));
@@ skipping 79 matching lines @@
         __ subs(result, left, Operand(right));
         __ b(deopt, VS);
       }
       break;
     }
     case Token::kMUL: {
       __ SmiUntag(IP, left);
       if (deopt == NULL) {
         __ mul(result, IP, right);
       } else {
-        if (TargetCPUFeatures::arm_version() == ARMv7) {
-          __ smull(result, IP, IP, right);
-          // IP: result bits 32..63.
-          __ cmp(IP, Operand(result, ASR, 31));
-          __ b(deopt, NE);
-        } else if (TargetCPUFeatures::can_divide()) {
-          const QRegister qtmp = locs()->temp(0).fpu_reg();
-          const DRegister dtmp0 = EvenDRegisterOf(qtmp);
-          const DRegister dtmp1 = OddDRegisterOf(qtmp);
-          __ CheckMultSignedOverflow(IP, right, result, dtmp0, dtmp1, deopt);
-          __ mul(result, IP, right);
-        } else {
-          // TODO(vegorov): never emit this instruction if hardware does not
-          // support it! This will lead to deopt cycle penalizing the code.
-          __ b(deopt);
-        }
+        __ smull(result, IP, IP, right);
+        // IP: result bits 32..63.
+        __ cmp(IP, Operand(result, ASR, 31));
+        __ b(deopt, NE);
       }
       break;
     }
     case Token::kBIT_AND: {
       // No overflow check.
       __ and_(result, left, Operand(right));
       break;
     }
     case Token::kBIT_OR: {
       // No overflow check.
       __ orr(result, left, Operand(right));
       break;
     }
     case Token::kBIT_XOR: {
       // No overflow check.
       __ eor(result, left, Operand(right));
       break;
     }
     case Token::kTRUNCDIV: {
+      ASSERT(TargetCPUFeatures::can_divide());
       if ((right_range == NULL) || right_range->Overlaps(0, 0)) {
         // Handle divide by zero in runtime.
         __ cmp(right, Operand(0));
         __ b(deopt, EQ);
       }
       const Register temp = locs()->temp(0).reg();
-      if (TargetCPUFeatures::can_divide()) {
-        const DRegister dtemp = EvenDRegisterOf(locs()->temp(1).fpu_reg());
-        __ SmiUntag(temp, left);
-        __ SmiUntag(IP, right);
-        __ IntegerDivide(result, temp, IP, dtemp, DTMP);
-      } else {
-        // TODO(vegorov): never emit this instruction if hardware does not
-        // support it! This will lead to deopt cycle penalizing the code.
-        __ b(deopt);
-      }
+      const DRegister dtemp = EvenDRegisterOf(locs()->temp(1).fpu_reg());
+      __ SmiUntag(temp, left);
+      __ SmiUntag(IP, right);
+      __ IntegerDivide(result, temp, IP, dtemp, DTMP);
 
       // Check the corner case of dividing the 'MIN_SMI' with -1, in which
       // case we cannot tag the result.
       __ CompareImmediate(result, 0x40000000);
       __ b(deopt, EQ);
       __ SmiTag(result);
       break;
     }
     case Token::kMOD: {
+      ASSERT(TargetCPUFeatures::can_divide());
       if ((right_range == NULL) || right_range->Overlaps(0, 0)) {
         // Handle divide by zero in runtime.
         __ cmp(right, Operand(0));
         __ b(deopt, EQ);
       }
       const Register temp = locs()->temp(0).reg();
-      if (TargetCPUFeatures::can_divide()) {
-        const DRegister dtemp = EvenDRegisterOf(locs()->temp(1).fpu_reg());
-        __ SmiUntag(temp, left);
-        __ SmiUntag(IP, right);
-        __ IntegerDivide(result, temp, IP, dtemp, DTMP);
-      } else {
-        // TODO(vegorov): never emit this instruction if hardware does not
-        // support it! This will lead to deopt cycle penalizing the code.
-        __ b(deopt);
-      }
+      const DRegister dtemp = EvenDRegisterOf(locs()->temp(1).fpu_reg());
+      __ SmiUntag(temp, left);
+      __ SmiUntag(IP, right);
+      __ IntegerDivide(result, temp, IP, dtemp, DTMP);
       __ SmiUntag(IP, right);
       __ mls(result, IP, result, temp);  // result <- left - right * result
       __ SmiTag(result);
       //  res = left % right;
       //  if (res < 0) {
       //    if (right < 0) {
       //      res = res - right;
       //    } else {
       //      res = res + right;
       //    }
@@ skipping 74 matching lines @@
 
 
 LocationSummary* BinaryInt32OpInstr::MakeLocationSummary(Zone* zone,
                                                          bool opt) const {
   const intptr_t kNumInputs = 2;
   // Calculate number of temporaries.
   intptr_t num_temps = 0;
   if (((op_kind() == Token::kSHL) && can_overflow()) ||
       (op_kind() == Token::kSHR)) {
     num_temps = 1;
-  } else if ((op_kind() == Token::kMUL) &&
-             (TargetCPUFeatures::arm_version() != ARMv7)) {
-    num_temps = 1;
   }
   LocationSummary* summary = new(zone) LocationSummary(
       zone, kNumInputs, num_temps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresRegister());
   summary->set_in(1, Location::RegisterOrSmiConstant(right()));
   if (((op_kind() == Token::kSHL) && can_overflow()) ||
       (op_kind() == Token::kSHR)) {
     summary->set_temp(0, Location::RequiresRegister());
   }
-  if (op_kind() == Token::kMUL) {
-    if (TargetCPUFeatures::arm_version() != ARMv7) {
-      summary->set_temp(0, Location::RequiresFpuRegister());
-    }
-  }
   // We make use of 3-operand instructions by not requiring result register
   // to be identical to first input register as on Intel.
   summary->set_out(0, Location::RequiresRegister());
   return summary;
 }
 
 
 void BinaryInt32OpInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   if (op_kind() == Token::kSHL) {
     EmitInt32ShiftLeft(compiler, this);
@@ skipping 30 matching lines @@
           __ SubImmediateSetFlags(result, left, value);
           __ b(deopt, VS);
         }
         break;
       }
       case Token::kMUL: {
         if (deopt == NULL) {
           __ LoadImmediate(IP, value);
           __ mul(result, left, IP);
         } else {
-          if (TargetCPUFeatures::arm_version() == ARMv7) {
-            __ LoadImmediate(IP, value);
-            __ smull(result, IP, left, IP);
-            // IP: result bits 32..63.
-            __ cmp(IP, Operand(result, ASR, 31));
-            __ b(deopt, NE);
-          } else if (TargetCPUFeatures::can_divide()) {
-            const QRegister qtmp = locs()->temp(0).fpu_reg();
-            const DRegister dtmp0 = EvenDRegisterOf(qtmp);
-            const DRegister dtmp1 = OddDRegisterOf(qtmp);
-            __ LoadImmediate(IP, value);
-            __ CheckMultSignedOverflow(left, IP, result, dtmp0, dtmp1, deopt);
-            __ mul(result, left, IP);
-          } else {
-            // TODO(vegorov): never emit this instruction if hardware does not
-            // support it! This will lead to deopt cycle penalizing the code.
-            __ b(deopt);
-          }
+          __ LoadImmediate(IP, value);
+          __ smull(result, IP, left, IP);
+          // IP: result bits 32..63.
+          __ cmp(IP, Operand(result, ASR, 31));
+          __ b(deopt, NE);
         }
         break;
       }
       case Token::kBIT_AND: {
         // No overflow check.
         Operand o;
         if (Operand::CanHold(value, &o)) {
           __ and_(result, left, o);
         } else if (Operand::CanHold(~value, &o)) {
           __ bic(result, left, o);
@@ skipping 56 matching lines @@
       } else {
         __ subs(result, left, Operand(right));
         __ b(deopt, VS);
       }
       break;
     }
     case Token::kMUL: {
       if (deopt == NULL) {
         __ mul(result, left, right);
       } else {
-        if (TargetCPUFeatures::arm_version() == ARMv7) {
-          __ smull(result, IP, left, right);
-          // IP: result bits 32..63.
-          __ cmp(IP, Operand(result, ASR, 31));
-          __ b(deopt, NE);
-        } else if (TargetCPUFeatures::can_divide()) {
-          const QRegister qtmp = locs()->temp(0).fpu_reg();
-          const DRegister dtmp0 = EvenDRegisterOf(qtmp);
-          const DRegister dtmp1 = OddDRegisterOf(qtmp);
-          __ CheckMultSignedOverflow(left, right, result, dtmp0, dtmp1, deopt);
-          __ mul(result, left, right);
-        } else {
-          // TODO(vegorov): never emit this instruction if hardware does not
-          // support it! This will lead to deopt cycle penalizing the code.
-          __ b(deopt);
-        }
+        __ smull(result, IP, left, right);
+        // IP: result bits 32..63.
+        __ cmp(IP, Operand(result, ASR, 31));
+        __ b(deopt, NE);
       }
       break;
     }
     case Token::kBIT_AND: {
       // No overflow check.
       __ and_(result, left, Operand(right));
       break;
     }
     case Token::kBIT_OR: {
       // No overflow check.
@@ skipping 2251 matching lines @@
   return NULL;
 }
 
 
 void MergedMathInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   Label* deopt = NULL;
   if (CanDeoptimize()) {
     deopt = compiler->AddDeoptStub(deopt_id(), ICData::kDeoptBinarySmiOp);
   }
   if (kind() == MergedMathInstr::kTruncDivMod) {
+    ASSERT(TargetCPUFeatures::can_divide());
     const Register left = locs()->in(0).reg();
     const Register right = locs()->in(1).reg();
     ASSERT(locs()->out(0).IsPairLocation());
     PairLocation* pair = locs()->out(0).AsPairLocation();
     const Register result_div = pair->At(0).reg();
     const Register result_mod = pair->At(1).reg();
     Range* right_range = InputAt(1)->definition()->range();
     if ((right_range == NULL) || right_range->Overlaps(0, 0)) {
       // Handle divide by zero in runtime.
       __ cmp(right, Operand(0));
       __ b(deopt, EQ);
     }
     const Register temp = locs()->temp(0).reg();
-    if (TargetCPUFeatures::can_divide()) {
-      const DRegister dtemp = EvenDRegisterOf(locs()->temp(1).fpu_reg());
-      __ SmiUntag(temp, left);
-      __ SmiUntag(IP, right);
-      __ IntegerDivide(result_div, temp, IP, dtemp, DTMP);
-    } else {
-      // TODO(vegorov): never emit this instruction if hardware does not
-      // support it! This will lead to deopt cycle penalizing the code.
-      __ b(deopt);
-    }
+    const DRegister dtemp = EvenDRegisterOf(locs()->temp(1).fpu_reg());
+    __ SmiUntag(temp, left);
+    __ SmiUntag(IP, right);
+    __ IntegerDivide(result_div, temp, IP, dtemp, DTMP);
 
     // Check the corner case of dividing the 'MIN_SMI' with -1, in which
     // case we cannot tag the result.
     __ CompareImmediate(result_div, 0x40000000);
     __ b(deopt, EQ);
     __ SmiUntag(IP, right);
     // result_mod <- left - right * result_div.
     __ mls(result_mod, IP, result_div, temp);
     __ SmiTag(result_div);
     __ SmiTag(result_mod);
@@ skipping 338 matching lines @@
         // Deopt on overflow.
         __ b(deopt, VS);
       }
       break;
     }
     case Token::kMUL: {
       // The product of two signed 32-bit integers fits in a signed 64-bit
       // result without causing overflow.
       // We deopt on larger inputs.
       // TODO(regis): Range analysis may eliminate the deopt check.
-      if (TargetCPUFeatures::arm_version() == ARMv7) {
-        __ cmp(left_hi, Operand(left_lo, ASR, 31));
-        __ cmp(right_hi, Operand(right_lo, ASR, 31), EQ);
-        __ b(deopt, NE);
-        __ smull(out_lo, out_hi, left_lo, right_lo);
-      } else {
-        // TODO(vegorov): never emit this instruction if hardware does not
-        // support it! This will lead to deopt cycle penalizing the code.
-        __ b(deopt);
-      }
+      __ cmp(left_hi, Operand(left_lo, ASR, 31));
+      __ cmp(right_hi, Operand(right_lo, ASR, 31), EQ);
+      __ b(deopt, NE);
+      __ smull(out_lo, out_hi, left_lo, right_lo);
       break;
     }
     default:
       UNREACHABLE();
   }
   if (FLAG_throw_on_javascript_int_overflow) {
     EmitJavascriptIntOverflowCheck(compiler, deopt, out_lo, out_hi);
   }
 }
 
@@ skipping 681 matching lines @@
                                 1,
                                 locs());
   __ Drop(1);
   __ Pop(result);
 }
 
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM