A few fixes for ARMv5TE.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 417 matching lines @@
     EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
   } else {
     mul(IP, rn, rm, cond);
     sub(rd, ra, Operand(IP), cond);
   }
 }
 
 
 void Assembler::smull(Register rd_lo, Register rd_hi,
                       Register rn, Register rm, Condition cond) {
-  ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
   // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
   EmitMulOp(cond, B23 | B22, rd_lo, rd_hi, rn, rm);
 }
 
 
 void Assembler::umull(Register rd_lo, Register rd_hi,
                       Register rn, Register rm, Condition cond) {
   ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
   // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
   EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm);
@@ skipping 84 matching lines @@
 void Assembler::ldrsb(Register rd, Address ad, Condition cond) {
   EmitMemOpAddressMode3(cond, L | B7 | B6 | B4, rd, ad);
 }
 
 
 void Assembler::ldrsh(Register rd, Address ad, Condition cond) {
   EmitMemOpAddressMode3(cond, L | B7 | B6 | H | B4, rd, ad);
 }
 
 
-void Assembler::ldrd(Register rd, Address ad, Condition cond) {
+void Assembler::ldrd(Register rd, Register rn, int32_t offset, Condition cond) {
   ASSERT((rd % 2) == 0);
-  EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, ad);
+  if (TargetCPUFeatures::arm_version() == ARMv5TE) {
+    const Register rd2 = static_cast<Register>(static_cast<int32_t>(rd) + 1);
+    ldr(rd, Address(rn, offset), cond);
+    ldr(rd2, Address(rn, offset + kWordSize), cond);
+  } else {
+    EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, Address(rn, offset));
+  }
 }
 
 
-void Assembler::strd(Register rd, Address ad, Condition cond) {
+void Assembler::strd(Register rd, Register rn, int32_t offset, Condition cond) {
   ASSERT((rd % 2) == 0);
-  EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, ad);
+  if (TargetCPUFeatures::arm_version() == ARMv5TE) {
+    const Register rd2 = static_cast<Register>(static_cast<int32_t>(rd) + 1);
+    str(rd, Address(rn, offset), cond);
+    str(rd2, Address(rn, offset + kWordSize), cond);
+  } else {
+    EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, Address(rn, offset));
+  }
 }
 
 
 void Assembler::ldm(BlockAddressMode am, Register base, RegList regs,
                     Condition cond) {
   ASSERT(regs != 0);
   EmitMultiMemOp(cond, am, true, base, regs);
-  if (TargetCPUFeatures::arm_version() == ARMv5TE) {
-    // On ARMv5, touching a "banked" register after an ldm gives undefined
-    // behavior, so we just add a nop here to make that case easy to avoid.
-    nop();
-  }
 }
 
 
 void Assembler::stm(BlockAddressMode am, Register base, RegList regs,
                     Condition cond) {
   ASSERT(regs != 0);
   EmitMultiMemOp(cond, am, false, base, regs);
-  if (TargetCPUFeatures::arm_version() == ARMv5TE) {
-    // On ARMv5, touching a "banked" register after an stm gives undefined
-    // behavior, so we just add a nop here to make that case easy to avoid.
-    nop();
-  }
 }
 
 
 void Assembler::ldrex(Register rt, Register rn, Condition cond) {
   ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE);
   ASSERT(rn != kNoRegister);
   ASSERT(rt != kNoRegister);
   ASSERT(cond != kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
                      B24 |
@@ skipping 1083 matching lines @@
                                        intptr_t offset,
                                        Register value_even,
                                        Register value_odd,
                                        Condition cond) {
   ASSERT(value_odd == value_even + 1);
   if (VerifiedMemory::enabled()) {
     ASSERT(base != value_even);
     ASSERT(base != value_odd);
     Operand shadow(GetVerifiedMemoryShadow());
     add(base, base, shadow, cond);
-    strd(value_even, Address(base, offset), cond);
+    strd(value_even, base, offset, cond);
     sub(base, base, shadow, cond);
   }
-  strd(value_even, Address(base, offset), cond);
+  strd(value_even, base, offset, cond);
 }
 
 
 Register UseRegister(Register reg, RegList* used) {
   ASSERT(reg != SP);
   ASSERT(reg != PC);
   ASSERT((*used & (1 << reg)) == 0);
   *used |= (1 << reg);
   return reg;
 }
@@ skipping 1094 matching lines @@
     case kHalfword:
       ldrsh(reg, Address(base, offset), cond);
       break;
     case kUnsignedHalfword:
       ldrh(reg, Address(base, offset), cond);
       break;
     case kWord:
       ldr(reg, Address(base, offset), cond);
       break;
     case kWordPair:
-      ldrd(reg, Address(base, offset), cond);
+      ldrd(reg, base, offset, cond);
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Assembler::StoreToOffset(OperandSize size,
                               Register reg,
                               Register base,
@@ skipping 11 matching lines @@
     case kByte:
       strb(reg, Address(base, offset), cond);
       break;
     case kHalfword:
       strh(reg, Address(base, offset), cond);
       break;
     case kWord:
       str(reg, Address(base, offset), cond);
       break;
     case kWordPair:
-      strd(reg, Address(base, offset), cond);
+      strd(reg, base, offset, cond);
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Assembler::LoadSFromOffset(SRegister reg,
                                 Register base,
                                 int32_t offset,
@@ skipping 285 matching lines @@
     vcvtdi(tmpl, stmpl);  // left is in tmpl.
     vmovsr(stmpr, right);
     vcvtdi(tmpr, stmpr);  // right is in tmpr.
     vdivd(tmpr, tmpl, tmpr);
     vcvtid(stmpr, tmpr);
     vmovrs(result, stmpr);
   }
 }
 
 
-// If we aren't on ARMv7, there is no smull, and we have to check for overflow
-// manually.
-void Assembler::CheckMultSignedOverflow(Register left,
-                                        Register right,
-                                        Register tmp,
-                                        DRegister dtmp0, DRegister dtmp1,
-                                        Label* overflow) {
-  Label done, left_neg, left_pos_right_neg, left_neg_right_pos;
-
-  CompareImmediate(left, 0);
-  b(&left_neg, LT);
-  b(&done, EQ);
-  CompareImmediate(right, 0);
-  b(&left_pos_right_neg, LT);
-  b(&done, EQ);
-
-  // Both positive.
-  LoadImmediate(tmp, INT_MAX);
-  IntegerDivide(tmp, tmp, left, dtmp0, dtmp1);
-  cmp(tmp, Operand(right));
-  b(overflow, LT);
-  b(&done);
-
-  // left positive, right non-positive.
-  Bind(&left_pos_right_neg);
-  LoadImmediate(tmp, INT_MIN);
-  IntegerDivide(tmp, tmp, left, dtmp0, dtmp1);
-  cmp(tmp, Operand(right));
-  b(overflow, GT);
-  b(&done);
-
-  Bind(&left_neg);
-  CompareImmediate(right, 0);
-  b(&left_neg_right_pos, GT);
-  b(&done, EQ);
-
-  // both negative.
-  LoadImmediate(tmp, INT_MAX);
-  IntegerDivide(tmp, tmp, left, dtmp0, dtmp1);
-  cmp(tmp, Operand(right));
-  b(overflow, GT);
-  b(&done);
-
-  // left non-positive, right positive.
-  Bind(&left_neg_right_pos);
-  LoadImmediate(tmp, INT_MIN);
-  IntegerDivide(tmp, tmp, right, dtmp0, dtmp1);
-  cmp(tmp, Operand(left));
-  b(overflow, GT);
-
-  Bind(&done);
-}
-
-
 static int NumRegsBelowFP(RegList regs) {
   int count = 0;
   for (int i = 0; i < FP; i++) {
     if ((regs & (1 << i)) != 0) {
       count++;
     }
   }
   return count;
 }
 
@@ skipping 117 matching lines @@
   AddImmediate(SP, -frame_size);
 }
 
 
 // On entry to a function compiled for OSR, the caller's frame pointer, the
 // stack locals, and any copied parameters are already in place.  The frame
 // pointer is already set up.  The PC marker is not correct for the
 // optimized function and there may be extra space for spill slots to
 // allocate. We must also set up the pool pointer for the function.
 void Assembler::EnterOsrFrame(intptr_t extra_size) {
-  const intptr_t offset = CodeSize();
+  // The offset for the PC marker is adjusted by the difference in PC offset
+  // between stores and other instructions. In particular, on some ARMv5's the
+  // PC offset for stores is 12 and the offset in other instructions is 8.
+  const intptr_t offset = CodeSize() -
+      (TargetCPUFeatures::store_pc_read_offset() - Instr::kPCReadOffset);
 
   Comment("EnterOsrFrame");
   mov(IP, Operand(PC));
 
   AddImmediate(IP, -offset);
   str(IP, Address(FP, kPcMarkerSlotFromFp * kWordSize));
 
   // Setup pool pointer for this dart function.
   LoadPoolPointer();
 
@@ skipping 294 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM