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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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892 break; | 892 break; |
893 case LBU: | 893 case LBU: |
894 Format(instr, "lbu 'rt, 'imm16s('rs)"); | 894 Format(instr, "lbu 'rt, 'imm16s('rs)"); |
895 break; | 895 break; |
896 case LHU: | 896 case LHU: |
897 Format(instr, "lhu 'rt, 'imm16s('rs)"); | 897 Format(instr, "lhu 'rt, 'imm16s('rs)"); |
898 break; | 898 break; |
899 case LWR: | 899 case LWR: |
900 Format(instr, "lwr 'rt, 'imm16s('rs)"); | 900 Format(instr, "lwr 'rt, 'imm16s('rs)"); |
901 break; | 901 break; |
| 902 case PREF: |
| 903 Format(instr, "pref 'rt, 'imm16s('rs)"); |
| 904 break; |
902 case SB: | 905 case SB: |
903 Format(instr, "sb 'rt, 'imm16s('rs)"); | 906 Format(instr, "sb 'rt, 'imm16s('rs)"); |
904 break; | 907 break; |
905 case SH: | 908 case SH: |
906 Format(instr, "sh 'rt, 'imm16s('rs)"); | 909 Format(instr, "sh 'rt, 'imm16s('rs)"); |
907 break; | 910 break; |
908 case SWL: | 911 case SWL: |
909 Format(instr, "swl 'rt, 'imm16s('rs)"); | 912 Format(instr, "swl 'rt, 'imm16s('rs)"); |
910 break; | 913 break; |
911 case SW: | 914 case SW: |
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1052 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 1055 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
1053 } | 1056 } |
1054 } | 1057 } |
1055 | 1058 |
1056 | 1059 |
1057 #undef UNSUPPORTED | 1060 #undef UNSUPPORTED |
1058 | 1061 |
1059 } // namespace disasm | 1062 } // namespace disasm |
1060 | 1063 |
1061 #endif // V8_TARGET_ARCH_MIPS | 1064 #endif // V8_TARGET_ARCH_MIPS |
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