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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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379 | 379 |
380 friend class Assembler; | 380 friend class Assembler; |
381 friend class MacroAssembler; | 381 friend class MacroAssembler; |
382 }; | 382 }; |
383 | 383 |
384 | 384 |
385 // On MIPS we have only one adressing mode with base_reg + offset. | 385 // On MIPS we have only one adressing mode with base_reg + offset. |
386 // Class MemOperand represents a memory operand in load and store instructions. | 386 // Class MemOperand represents a memory operand in load and store instructions. |
387 class MemOperand : public Operand { | 387 class MemOperand : public Operand { |
388 public: | 388 public: |
| 389 // Immediate value attached to offset. |
| 390 enum OffsetAddend { |
| 391 offset_minus_one = -1, |
| 392 offset_zero = 0 |
| 393 }; |
| 394 |
389 explicit MemOperand(Register rn, int32_t offset = 0); | 395 explicit MemOperand(Register rn, int32_t offset = 0); |
| 396 explicit MemOperand(Register rn, int32_t unit, int32_t multiplier, |
| 397 OffsetAddend offset_addend = offset_zero); |
390 int32_t offset() const { return offset_; } | 398 int32_t offset() const { return offset_; } |
391 | 399 |
392 bool OffsetIsInt16Encodable() const { | 400 bool OffsetIsInt16Encodable() const { |
393 return is_int16(offset_); | 401 return is_int16(offset_); |
394 } | 402 } |
395 | 403 |
396 private: | 404 private: |
397 int32_t offset_; | 405 int32_t offset_; |
398 | 406 |
399 friend class Assembler; | 407 friend class Assembler; |
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704 void lw(Register rd, const MemOperand& rs); | 712 void lw(Register rd, const MemOperand& rs); |
705 void lwl(Register rd, const MemOperand& rs); | 713 void lwl(Register rd, const MemOperand& rs); |
706 void lwr(Register rd, const MemOperand& rs); | 714 void lwr(Register rd, const MemOperand& rs); |
707 void sb(Register rd, const MemOperand& rs); | 715 void sb(Register rd, const MemOperand& rs); |
708 void sh(Register rd, const MemOperand& rs); | 716 void sh(Register rd, const MemOperand& rs); |
709 void sw(Register rd, const MemOperand& rs); | 717 void sw(Register rd, const MemOperand& rs); |
710 void swl(Register rd, const MemOperand& rs); | 718 void swl(Register rd, const MemOperand& rs); |
711 void swr(Register rd, const MemOperand& rs); | 719 void swr(Register rd, const MemOperand& rs); |
712 | 720 |
713 | 721 |
| 722 //----------------Prefetch-------------------- |
| 723 |
| 724 void pref(int32_t hint, const MemOperand& rs); |
| 725 |
| 726 |
714 //-------------Misc-instructions-------------- | 727 //-------------Misc-instructions-------------- |
715 | 728 |
716 // Break / Trap instructions. | 729 // Break / Trap instructions. |
717 void break_(uint32_t code, bool break_as_stop = false); | 730 void break_(uint32_t code, bool break_as_stop = false); |
718 void stop(const char* msg, uint32_t code = kMaxStopCode); | 731 void stop(const char* msg, uint32_t code = kMaxStopCode); |
719 void tge(Register rs, Register rt, uint16_t code); | 732 void tge(Register rs, Register rt, uint16_t code); |
720 void tgeu(Register rs, Register rt, uint16_t code); | 733 void tgeu(Register rs, Register rt, uint16_t code); |
721 void tlt(Register rs, Register rt, uint16_t code); | 734 void tlt(Register rs, Register rt, uint16_t code); |
722 void tltu(Register rs, Register rt, uint16_t code); | 735 void tltu(Register rs, Register rt, uint16_t code); |
723 void teq(Register rs, Register rt, uint16_t code); | 736 void teq(Register rs, Register rt, uint16_t code); |
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1234 class EnsureSpace BASE_EMBEDDED { | 1247 class EnsureSpace BASE_EMBEDDED { |
1235 public: | 1248 public: |
1236 explicit EnsureSpace(Assembler* assembler) { | 1249 explicit EnsureSpace(Assembler* assembler) { |
1237 assembler->CheckBuffer(); | 1250 assembler->CheckBuffer(); |
1238 } | 1251 } |
1239 }; | 1252 }; |
1240 | 1253 |
1241 } } // namespace v8::internal | 1254 } } // namespace v8::internal |
1242 | 1255 |
1243 #endif // V8_ARM_ASSEMBLER_MIPS_H_ | 1256 #endif // V8_ARM_ASSEMBLER_MIPS_H_ |
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