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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_X64_ASSEMBLER_X64_INL_H_ | 5 #ifndef V8_X64_ASSEMBLER_X64_INL_H_ |
6 #define V8_X64_ASSEMBLER_X64_INL_H_ | 6 #define V8_X64_ASSEMBLER_X64_INL_H_ |
7 | 7 |
8 #include "src/x64/assembler-x64.h" | 8 #include "src/x64/assembler-x64.h" |
9 | 9 |
10 #include "src/base/cpu.h" | 10 #include "src/base/cpu.h" |
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227 emit_vex3_byte0(); | 227 emit_vex3_byte0(); |
228 emit_vex3_byte1(reg, rm, mm); | 228 emit_vex3_byte1(reg, rm, mm); |
229 emit_vex3_byte2(w, vreg, l, pp); | 229 emit_vex3_byte2(w, vreg, l, pp); |
230 } else { | 230 } else { |
231 emit_vex2_byte0(); | 231 emit_vex2_byte0(); |
232 emit_vex2_byte1(reg, vreg, l, pp); | 232 emit_vex2_byte1(reg, vreg, l, pp); |
233 } | 233 } |
234 } | 234 } |
235 | 235 |
236 | 236 |
| 237 void Assembler::emit_vex_prefix(Register reg, Register vreg, Register rm, |
| 238 VectorLength l, SIMDPrefix pp, LeadingOpcode mm, |
| 239 VexW w) { |
| 240 XMMRegister ireg = {reg.code()}; |
| 241 XMMRegister ivreg = {vreg.code()}; |
| 242 XMMRegister irm = {rm.code()}; |
| 243 emit_vex_prefix(ireg, ivreg, irm, l, pp, mm, w); |
| 244 } |
| 245 |
| 246 |
237 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, | 247 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, |
238 const Operand& rm, VectorLength l, | 248 const Operand& rm, VectorLength l, |
239 SIMDPrefix pp, LeadingOpcode mm, VexW w) { | 249 SIMDPrefix pp, LeadingOpcode mm, VexW w) { |
240 if (rm.rex_ || mm != k0F || w != kW0) { | 250 if (rm.rex_ || mm != k0F || w != kW0) { |
241 emit_vex3_byte0(); | 251 emit_vex3_byte0(); |
242 emit_vex3_byte1(reg, rm, mm); | 252 emit_vex3_byte1(reg, rm, mm); |
243 emit_vex3_byte2(w, vreg, l, pp); | 253 emit_vex3_byte2(w, vreg, l, pp); |
244 } else { | 254 } else { |
245 emit_vex2_byte0(); | 255 emit_vex2_byte0(); |
246 emit_vex2_byte1(reg, vreg, l, pp); | 256 emit_vex2_byte1(reg, vreg, l, pp); |
247 } | 257 } |
248 } | 258 } |
249 | 259 |
250 | 260 |
| 261 void Assembler::emit_vex_prefix(Register reg, Register vreg, const Operand& rm, |
| 262 VectorLength l, SIMDPrefix pp, LeadingOpcode mm, |
| 263 VexW w) { |
| 264 XMMRegister ireg = {reg.code()}; |
| 265 XMMRegister ivreg = {vreg.code()}; |
| 266 emit_vex_prefix(ireg, ivreg, rm, l, pp, mm, w); |
| 267 } |
| 268 |
| 269 |
251 Address Assembler::target_address_at(Address pc, | 270 Address Assembler::target_address_at(Address pc, |
252 ConstantPoolArray* constant_pool) { | 271 ConstantPoolArray* constant_pool) { |
253 return Memory::int32_at(pc) + pc + 4; | 272 return Memory::int32_at(pc) + pc + 4; |
254 } | 273 } |
255 | 274 |
256 | 275 |
257 void Assembler::set_target_address_at(Address pc, | 276 void Assembler::set_target_address_at(Address pc, |
258 ConstantPoolArray* constant_pool, | 277 ConstantPoolArray* constant_pool, |
259 Address target, | 278 Address target, |
260 ICacheFlushMode icache_flush_mode) { | 279 ICacheFlushMode icache_flush_mode) { |
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644 | 663 |
645 void Operand::set_disp64(int64_t disp) { | 664 void Operand::set_disp64(int64_t disp) { |
646 DCHECK_EQ(1, len_); | 665 DCHECK_EQ(1, len_); |
647 int64_t* p = reinterpret_cast<int64_t*>(&buf_[len_]); | 666 int64_t* p = reinterpret_cast<int64_t*>(&buf_[len_]); |
648 *p = disp; | 667 *p = disp; |
649 len_ += sizeof(disp); | 668 len_ += sizeof(disp); |
650 } | 669 } |
651 } } // namespace v8::internal | 670 } } // namespace v8::internal |
652 | 671 |
653 #endif // V8_X64_ASSEMBLER_X64_INL_H_ | 672 #endif // V8_X64_ASSEMBLER_X64_INL_H_ |
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