[x64] Introduce BMI instructions.

src/x64/assembler-x64-inl.h

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_X64_ASSEMBLER_X64_INL_H_
 #define V8_X64_ASSEMBLER_X64_INL_H_
 
 #include "src/x64/assembler-x64.h"
 
 #include "src/base/cpu.h"
@@ skipping 216 matching lines @@
     emit_vex3_byte0();
     emit_vex3_byte1(reg, rm, mm);
     emit_vex3_byte2(w, vreg, l, pp);
   } else {
     emit_vex2_byte0();
     emit_vex2_byte1(reg, vreg, l, pp);
   }
 }
 
 
+void Assembler::emit_vex_prefix(Register reg, Register vreg, Register rm,
+                                VectorLength l, SIMDPrefix pp, LeadingOpcode mm,
+                                VexW w) {
+  XMMRegister ireg = {reg.code()};
+  XMMRegister ivreg = {vreg.code()};
+  XMMRegister irm = {rm.code()};
+  emit_vex_prefix(ireg, ivreg, irm, l, pp, mm, w);
+}
+
+
 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg,
                                 const Operand& rm, VectorLength l,
                                 SIMDPrefix pp, LeadingOpcode mm, VexW w) {
   if (rm.rex_ || mm != k0F || w != kW0) {
     emit_vex3_byte0();
     emit_vex3_byte1(reg, rm, mm);
     emit_vex3_byte2(w, vreg, l, pp);
   } else {
     emit_vex2_byte0();
     emit_vex2_byte1(reg, vreg, l, pp);
   }
 }
 
 
+void Assembler::emit_vex_prefix(Register reg, Register vreg, const Operand& rm,
+                                VectorLength l, SIMDPrefix pp, LeadingOpcode mm,
+                                VexW w) {
+  XMMRegister ireg = {reg.code()};
+  XMMRegister ivreg = {vreg.code()};
+  emit_vex_prefix(ireg, ivreg, rm, l, pp, mm, w);
+}
+
+
 Address Assembler::target_address_at(Address pc,
                                      ConstantPoolArray* constant_pool) {
   return Memory::int32_at(pc) + pc + 4;
 }
 
 
 void Assembler::set_target_address_at(Address pc,
                                       ConstantPoolArray* constant_pool,
                                       Address target,
                                       ICacheFlushMode icache_flush_mode) {
@@ skipping 383 matching lines @@
 
 void Operand::set_disp64(int64_t disp) {
   DCHECK_EQ(1, len_);
   int64_t* p = reinterpret_cast<int64_t*>(&buf_[len_]);
   *p = disp;
   len_ += sizeof(disp);
 }
 } }  // namespace v8::internal
 
 #endif  // V8_X64_ASSEMBLER_X64_INL_H_