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Side by Side Diff: src/compiler/ppc/instruction-codes-ppc.h

Issue 1028313003: PPC: [turbofan] Turn Math.clz32 into an inlinable builtin. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 9 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ 5 #ifndef V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_
6 #define V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ 6 #define V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 51 matching lines...) Expand 10 before | Expand all | Expand 10 after
62 V(PPC_Neg32) \ 62 V(PPC_Neg32) \
63 V(PPC_Neg64) \ 63 V(PPC_Neg64) \
64 V(PPC_NegFloat64) \ 64 V(PPC_NegFloat64) \
65 V(PPC_SqrtFloat64) \ 65 V(PPC_SqrtFloat64) \
66 V(PPC_FloorFloat64) \ 66 V(PPC_FloorFloat64) \
67 V(PPC_CeilFloat64) \ 67 V(PPC_CeilFloat64) \
68 V(PPC_TruncateFloat64) \ 68 V(PPC_TruncateFloat64) \
69 V(PPC_RoundFloat64) \ 69 V(PPC_RoundFloat64) \
70 V(PPC_MaxFloat64) \ 70 V(PPC_MaxFloat64) \
71 V(PPC_MinFloat64) \ 71 V(PPC_MinFloat64) \
72 V(PPC_Cntlz32) \
72 V(PPC_Cmp32) \ 73 V(PPC_Cmp32) \
73 V(PPC_Cmp64) \ 74 V(PPC_Cmp64) \
74 V(PPC_CmpFloat64) \ 75 V(PPC_CmpFloat64) \
75 V(PPC_Tst32) \ 76 V(PPC_Tst32) \
76 V(PPC_Tst64) \ 77 V(PPC_Tst64) \
77 V(PPC_Push) \ 78 V(PPC_Push) \
78 V(PPC_ExtendSignWord8) \ 79 V(PPC_ExtendSignWord8) \
79 V(PPC_ExtendSignWord16) \ 80 V(PPC_ExtendSignWord16) \
80 V(PPC_ExtendSignWord32) \ 81 V(PPC_ExtendSignWord32) \
81 V(PPC_Uint32ToUint64) \ 82 V(PPC_Uint32ToUint64) \
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after
123 // MRR = [register + register] 124 // MRR = [register + register]
124 #define TARGET_ADDRESSING_MODE_LIST(V) \ 125 #define TARGET_ADDRESSING_MODE_LIST(V) \
125 V(MRI) /* [%r0 + K] */ \ 126 V(MRI) /* [%r0 + K] */ \
126 V(MRR) /* [%r0 + %r1] */ 127 V(MRR) /* [%r0 + %r1] */
127 128
128 } // namespace compiler 129 } // namespace compiler
129 } // namespace internal 130 } // namespace internal
130 } // namespace v8 131 } // namespace v8
131 132
132 #endif // V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ 133 #endif // V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_
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