Add divide to Sk2x, use native vdiv and vsqrt on ARM 64.

src/opts/Sk4x_neon.h

 // It is important _not_ to put header guards here.
 // This file will be intentionally included three times.
 
 #include "SkTypes.h"  // Keep this before any #ifdef for skbug.com/3362
 
 #if defined(SK4X_PREAMBLE)
     #include <arm_neon.h>
 
     // Template metaprogramming to map scalar types to vector types.
     template <typename T> struct SkScalarToSIMD;
@@ skipping 57 matching lines @@
 M(Sk4i) cast<Sk4i>() const { return vcvtq_s32_f32(fVec); }
 
 // We're going to skip allTrue(), anyTrue(), and bit-manipulators
 // for Sk4f.  Code that calls them probably does so accidentally.
 // Ask msarett or mtklein to fill these in if you really need them.
 M(Sk4f) add     (const Sk4f& o) const { return vaddq_f32(fVec, o.fVec); }
 M(Sk4f) subtract(const Sk4f& o) const { return vsubq_f32(fVec, o.fVec); }
 M(Sk4f) multiply(const Sk4f& o) const { return vmulq_f32(fVec, o.fVec); }
 
 M(Sk4f) divide  (const Sk4f& o) const {
-    float32x4_t est0 = vrecpeq_f32(o.fVec);
-    float32x4_t est1 = vmulq_f32(vrecpsq_f32(est0, o.fVec), est0);
-    float32x4_t est2 = vmulq_f32(vrecpsq_f32(est1, o.fVec), est1);
+#if defined(SK_CPU_ARM64)
+    return vdivq_f32(fVec, o.fVec);
+#else
+    float32x4_t est0 = vrecpeq_f32(o.fVec),
+                est1 = vmulq_f32(vrecpsq_f32(est0, o.fVec), est0),
+                est2 = vmulq_f32(vrecpsq_f32(est1, o.fVec), est1);
     return vmulq_f32(est2, fVec);
+#endif
 }
 
 M(Sk4f) rsqrt() const {
     float32x4_t est0 = vrsqrteq_f32(fVec),
                 est1 = vmulq_f32(vrsqrtsq_f32(fVec, vmulq_f32(est0, est0)), est0);
     return est1;
 }
 
 M(Sk4f)  sqrt() const {
+#if defined(SK_CPU_ARM64)
+    return vsqrtq_f32(fVec);
+#else
     float32x4_t est1 = this->rsqrt().fVec,
     // An extra step of Newton's method to refine the estimate of 1/sqrt(this).
                 est2 = vmulq_f32(vrsqrtsq_f32(fVec, vmulq_f32(est1, est1)), est1);
     return vmulq_f32(fVec, est2);
+#endif
 }
 
 M(Sk4i) equal           (const Sk4f& o) const { return vreinterpretq_s32_u32(vceqq_f32(fVec, o.fVec)); }
 M(Sk4i) notEqual        (const Sk4f& o) const { return vreinterpretq_s32_u32(vmvnq_u32(vceqq_f32(fVec, o.fVec))); }
 M(Sk4i) lessThan        (const Sk4f& o) const { return vreinterpretq_s32_u32(vcltq_f32(fVec, o.fVec)); }
 M(Sk4i) greaterThan     (const Sk4f& o) const { return vreinterpretq_s32_u32(vcgtq_f32(fVec, o.fVec)); }
 M(Sk4i) lessThanEqual   (const Sk4f& o) const { return vreinterpretq_s32_u32(vcleq_f32(fVec, o.fVec)); }
 M(Sk4i) greaterThanEqual(const Sk4f& o) const { return vreinterpretq_s32_u32(vcgeq_f32(fVec, o.fVec)); }
 
 M(Sk4f) Min(const Sk4f& a, const Sk4f& b) { return vminq_f32(a.fVec, b.fVec); }
@@ skipping 112 matching lines @@
 }
 M(Sk4i) ZWCD(const Sk4i& xyzw, const Sk4i& abcd) {
     int32x4x2_t xayb_zcwd = vzipq_s32(xyzw.fVec, abcd.fVec);
     int32x4x2_t axby_czdw = vzipq_s32(abcd.fVec, xyzw.fVec);
     return vuzpq_s32(xayb_zcwd.val[1], axby_czdw.val[1]).val[0];
 }
 
 #undef M
 
 #endif