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Unified Diff: src/compiler/mips/code-generator-mips.cc

Issue 1027193002: MIPS64: [turbofan] Support Float64Min and Float64Max. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Add bodies of 32 bits visitor()'s. Created 5 years, 7 months ago
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Index: src/compiler/mips/code-generator-mips.cc
diff --git a/src/compiler/mips/code-generator-mips.cc b/src/compiler/mips/code-generator-mips.cc
index 0e45172a5b9919496dbfd927adfbaff4fd60d05c..04611903cf46dca12afbafb2287a180637b96c55 100644
--- a/src/compiler/mips/code-generator-mips.cc
+++ b/src/compiler/mips/code-generator-mips.cc
@@ -622,6 +622,14 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ sqrt_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
break;
}
+ case kMipsMaxS:
+ __ max_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
+ i.InputDoubleRegister(1));
+ break;
+ case kMipsMinS:
+ __ min_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
+ i.InputDoubleRegister(1));
+ break;
case kMipsCmpD:
// Psuedo-instruction used for FP cmp/branch. No opcode emitted here.
break;
@@ -663,6 +671,14 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ sqrt_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
break;
}
+ case kMipsMaxD:
+ __ max_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
+ i.InputDoubleRegister(1));
+ break;
+ case kMipsMinD:
+ __ min_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
+ i.InputDoubleRegister(1));
+ break;
case kMipsFloat64RoundDown: {
ASSEMBLE_ROUND_DOUBLE_TO_DOUBLE(floor_l_d, Floor);
break;
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