Subzero: Don't use key SSE instructions on potentially unaligned loads.

src/IceTargetLoweringX8632.cpp

Index: src/IceTargetLoweringX8632.cpp
diff --git a/src/IceTargetLoweringX8632.cpp b/src/IceTargetLoweringX8632.cpp
index 84333b45ef3f8b50b7eade4d65bf079e721de3c0..c1c40368f4a70cbd283bd77da48caf44eb04c171 100644
--- a/src/IceTargetLoweringX8632.cpp
+++ b/src/IceTargetLoweringX8632.cpp
@@ -1375,6 +1375,8 @@ void TargetX8632::lowerArithmetic(const InstArithmetic *Inst) {
   } else if (isVectorType(Dest->getType())) {
     // TODO: Trap on integer divide and integer modulo by zero.
     // See: https://code.google.com/p/nativeclient/issues/detail?id=3899
+    if (llvm::isa<OperandX8632Mem>(Src1))
+      Src1 = legalizeToVar(Src1);
     switch (Inst->getOp()) {
     case InstArithmetic::_num:
       llvm_unreachable("Unknown arithmetic operator");
@@ -2090,6 +2092,8 @@ void TargetX8632::lowerCast(const InstCast *Inst) {
       assert(Dest->getType() == IceType_v4i32 &&
              Inst->getSrc(0)->getType() == IceType_v4f32);
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
+      if (llvm::isa<OperandX8632Mem>(Src0RM))
+        Src0RM = legalizeToVar(Src0RM);
       Variable *T = makeReg(Dest->getType());
       _cvt(T, Src0RM, InstX8632Cvt::Tps2dq);
       _movp(Dest, T);
@@ -2165,6 +2169,8 @@ void TargetX8632::lowerCast(const InstCast *Inst) {
       assert(Dest->getType() == IceType_v4f32 &&
              Inst->getSrc(0)->getType() == IceType_v4i32);
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
+      if (llvm::isa<OperandX8632Mem>(Src0RM))
+        Src0RM = legalizeToVar(Src0RM);
       Variable *T = makeReg(Dest->getType());
       _cvt(T, Src0RM, InstX8632Cvt::Dq2ps);
       _movp(Dest, T);
@@ -2472,6 +2478,8 @@ void TargetX8632::lowerFcmp(const InstFcmp *Inst) {
     } else {
       Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
       Operand *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
+      if (llvm::isa<OperandX8632Mem>(Src1RM))
+        Src1RM = legalizeToVar(Src1RM);
 
       switch (Condition) {
       default: {
@@ -2586,6 +2594,10 @@ void TargetX8632::lowerIcmp(const InstIcmp *Inst) {
 
     Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
     Operand *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
+    if (llvm::isa<OperandX8632Mem>(Src0RM))

[jvoung (off chromium), 2015/03/23 21:30:35]

Vs the other places where only Src1RM is legalized here both 0 and 1 are
legalized:

(*) other places already have a _movp(T, Src0RM)
(*) here most cases also have a _movp(T, Src0RM), but sometimes the operands are
swapped and instead _movp(T, Src1RM) is done.
(*) The extra _movp / legalize should be optimized out as redundant.

[Jim Stichnoth, 2015/03/23 22:10:03]

Done - pushed the appropriate legalization into each specific case, for better
precision.

+      Src0RM = legalizeToVar(Src0RM);
+    if (llvm::isa<OperandX8632Mem>(Src1RM))
+      Src1RM = legalizeToVar(Src1RM);
 
     // SSE2 only has signed comparison operations.  Transform unsigned
     // inputs in a manner that allows for the use of signed comparison
@@ -3092,8 +3104,12 @@ void TargetX8632::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
     Variable *T = makeVectorOfFabsMask(Ty);
     // The pand instruction operates on an m128 memory operand, so if
     // Src is an f32 or f64, we need to make sure it's in a register.
-    if (!isVectorType(Ty))
+    if (isVectorType(Ty)) {
+      if (llvm::isa<OperandX8632Mem>(Src))
+        Src = legalizeToVar(Src);
+    } else {
       Src = legalizeToVar(Src);
+    }
     _pand(T, Src);
     if (isVectorType(Ty))
       _movp(Dest, T);