Subzero: Don't use key SSE instructions on potentially unaligned loads.

src/IceInstX8632.h

 //===- subzero/src/IceInstX8632.h - Low-level x86 instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file declares the InstX8632 and OperandX8632 classes and
@@ skipping 255 matching lines @@
   static const char *getFldString(Type Ty);
   void dump(const Cfg *Func) const override;
 
 protected:
   InstX8632(Cfg *Func, InstKindX8632 Kind, SizeT Maxsrcs, Variable *Dest)
       : InstTarget(Func, static_cast<InstKind>(Kind), Maxsrcs, Dest) {}
   ~InstX8632() override {}
   static bool isClassof(const Inst *Inst, InstKindX8632 MyKind) {
     return Inst->getKind() == static_cast<InstKind>(MyKind);
   }
+  // Most instructions that operate on vector arguments require vector
+  // memory operands to be fully aligned (16-byte alignment for PNaCl
+  // vector types).  The stack frame layout and call ABI ensure proper
+  // alignment for stack operands, but memory operands (originating
+  // from load/store bitcode instructions) only have element-size
+  // alignment guarantees.  This function validates that none of the
+  // operands is a memory operand of vector type, calling
+  // report_fatal_error() if one is found.  This function should be
+  // called during emission, and maybe also in the ctor (as long as
+  // that fits the lowering style).
+  void validateVectorAddrMode() const {
+    if (getDest())
+      validateVectorAddrModeOpnd(getDest());
+    for (SizeT i = 0; i < getSrcSize(); ++i) {
+      validateVectorAddrModeOpnd(getSrc(i));
+    }
+  }
+private:
+  static void validateVectorAddrModeOpnd(const Operand *Opnd) {
+    if (llvm::isa<OperandX8632Mem>(Opnd) && isVectorType(Opnd->getType())) {
+      llvm::report_fatal_error("Possible misaligned vector memory operation");
+    }
+  }
 };
 
 // InstX8632Label represents an intra-block label that is the target
 // of an intra-block branch.  The offset between the label and the
 // branch must be fit into one byte (considered "near").  These are
 // used for lowering i1 calculations, Select instructions, and 64-bit
 // compares on a 32-bit architecture, without basic block splitting.
 // Basic block splitting is not so desirable for several reasons, one
 // of which is the impact on decisions based on whether a variable's
 // live range spans multiple basic blocks.
@@ skipping 459 matching lines @@
 
 public:
   // Create an XMM binary-op instruction like addss or addps.
   static InstX8632BinopXmm *create(Cfg *Func, Variable *Dest, Operand *Source) {
     return new (Func->allocate<InstX8632BinopXmm>())
         InstX8632BinopXmm(Func, Dest, Source);
   }
   void emit(const Cfg *Func) const override {
     if (!ALLOW_DUMP)
       return;
+    validateVectorAddrMode();
     const bool ShiftHack = false;
     emitTwoAddress(Opcode, this, Func, ShiftHack);
   }
   void emitIAS(const Cfg *Func) const override {
+    validateVectorAddrMode();
     Type Ty = getDest()->getType();
     if (NeedsElementType)
       Ty = typeElementType(Ty);
     assert(getSrcSize() == 2);
     emitIASRegOpTyXMM(Func, Ty, getDest(), getSrc(1), Emitter);
   }
   void dump(const Cfg *Func) const override {
     if (!ALLOW_DUMP)
       return;
     Ostream &Str = Func->getContext()->getStrDump();
@@ skipping 27 matching lines @@
 public:
   // Create an XMM binary-op shift operation.
   static InstX8632BinopXmmShift *create(Cfg *Func, Variable *Dest,
                                         Operand *Source) {
     return new (Func->allocate<InstX8632BinopXmmShift>())
         InstX8632BinopXmmShift(Func, Dest, Source);
   }
   void emit(const Cfg *Func) const override {
     if (!ALLOW_DUMP)
       return;
+    validateVectorAddrMode();
     const bool ShiftHack = false;
     emitTwoAddress(Opcode, this, Func, ShiftHack);
   }
   void emitIAS(const Cfg *Func) const override {
+    validateVectorAddrMode();
     Type Ty = getDest()->getType();
     assert(AllowAllTypes || isVectorType(Ty));
     Type ElementTy = typeElementType(Ty);
     assert(getSrcSize() == 2);
     emitIASXmmShift(Func, ElementTy, getDest(), getSrc(1), Emitter);
   }
   void dump(const Cfg *Func) const override {
     if (!ALLOW_DUMP)
       return;
     Ostream &Str = Func->getContext()->getStrDump();
@@ skipping 831 matching lines @@
 template <> void InstX8632Pinsr::emitIAS(const Cfg *Func) const;
 template <> void InstX8632Movsx::emitIAS(const Cfg *Func) const;
 template <> void InstX8632Movzx::emitIAS(const Cfg *Func) const;
 template <> void InstX8632Pmull::emitIAS(const Cfg *Func) const;
 template <> void InstX8632Pshufd::emitIAS(const Cfg *Func) const;
 template <> void InstX8632Shufps::emitIAS(const Cfg *Func) const;
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTX8632_H