Move some flag-like props from GlobalContext and TargetLowering to ClFlags.

src/IceTargetLoweringX8632.cpp

 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetLoweringX8632 class, which
 // consists almost entirely of the lowering sequence for each
 // high-level instruction.
 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/MathExtras.h"
 
 #include "IceCfg.h"
 #include "IceCfgNode.h"
 #include "IceClFlags.h"
 #include "IceDefs.h"
 #include "IceELFObjectWriter.h"
 #include "IceGlobalInits.h"
 #include "IceInstX8632.h"
 #include "IceLiveness.h"
@@ skipping 119 matching lines @@
   assert((Alignment & (Alignment - 1)) == 0);
   return (Value + Alignment - 1) & -Alignment;
 }
 
 // Value is in bytes. Return Value adjusted to the next highest multiple
 // of the stack alignment.
 uint32_t applyStackAlignment(uint32_t Value) {
   return applyAlignment(Value, X86_STACK_ALIGNMENT_BYTES);
 }
 
-// Instruction set options
-namespace cl = ::llvm::cl;
-cl::opt<TargetX8632::X86InstructionSet> CLInstructionSet(
-    "mattr", cl::desc("X86 target attributes"), cl::init(TargetX8632::SSE2),
-    cl::values(clEnumValN(TargetX8632::SSE2, "sse2",
-                          "Enable SSE2 instructions (default)"),
-               clEnumValN(TargetX8632::SSE4_1, "sse4.1",
-                          "Enable SSE 4.1 instructions"),
-               clEnumValEnd));
-
 // In some cases, there are x-macros tables for both high-level and
 // low-level instructions/operands that use the same enum key value.
 // The tables are kept separate to maintain a proper separation
 // between abstraction layers.  There is a risk that the tables could
 // get out of sync if enum values are reordered or if entries are
 // added or deleted.  The following dummy namespaces use
 // static_asserts to ensure everything is kept in sync.
 
 // Validate the enum values in FCMPX8632_TABLE.
 namespace dummy1 {
@@ skipping 89 matching lines @@
 #define X(tag, size, align, elts, elty, str)                                   \
   static_assert(_table1_##tag == _table2_##tag,                                \
                 "Inconsistency between ICETYPEX8632_TABLE and ICETYPE_TABLE");
 ICETYPE_TABLE
 #undef X
 } // end of namespace dummy3
 
 } // end of anonymous namespace
 
 TargetX8632::TargetX8632(Cfg *Func)
-    : TargetLowering(Func), InstructionSet(CLInstructionSet),
+    : TargetLowering(Func),
+      InstructionSet(static_cast<X86InstructionSet>(
+          Func->getContext()->getFlags().getTargetInstructionSet() -
+          TargetInstructionSet::X86InstructionSet_Begin)),
       IsEbpBasedFrame(false), NeedsStackAlignment(false), FrameSizeLocals(0),
       SpillAreaSizeBytes(0), NextLabelNumber(0) {
+  static_assert((X86InstructionSet::End - X86InstructionSet::Begin) ==
+                    (TargetInstructionSet::X86InstructionSet_End -
+                     TargetInstructionSet::X86InstructionSet_Begin),
+                "X86InstructionSet range different from TargetInstructionSet");
   // TODO: Don't initialize IntegerRegisters and friends every time.
   // Instead, initialize in some sort of static initializer for the
   // class.
   llvm::SmallBitVector IntegerRegisters(RegX8632::Reg_NUM);
   llvm::SmallBitVector IntegerRegistersI8(RegX8632::Reg_NUM);
   llvm::SmallBitVector FloatRegisters(RegX8632::Reg_NUM);
   llvm::SmallBitVector VectorRegisters(RegX8632::Reg_NUM);
   llvm::SmallBitVector InvalidRegisters(RegX8632::Reg_NUM);
   ScratchRegs.resize(RegX8632::Reg_NUM);
 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
@@ skipping 105 matching lines @@
 
   // Branch optimization.  This needs to be done just before code
   // emission.  In particular, no transformations that insert or
   // reorder CfgNodes should be done after branch optimization.  We go
   // ahead and do it before nop insertion to reduce the amount of work
   // needed for searching for opportunities.
   Func->doBranchOpt();
   Func->dump("After branch optimization");
 
   // Nop insertion
-  if (shouldDoNopInsertion()) {
+  if (Ctx->getFlags().shouldDoNopInsertion()) {
     Func->doNopInsertion();
   }
 }
 
 void TargetX8632::translateOm1() {
   TimerMarker T(TimerStack::TT_Om1, Func);
 
   Func->placePhiLoads();
   if (Func->hasError())
     return;
@@ skipping 16 matching lines @@
   if (Func->hasError())
     return;
   Func->dump("After regalloc of infinite-weight variables");
 
   Func->genFrame();
   if (Func->hasError())
     return;
   Func->dump("After stack frame mapping");
 
   // Nop insertion
-  if (shouldDoNopInsertion()) {
+  if (Ctx->getFlags().shouldDoNopInsertion()) {
     Func->doNopInsertion();
   }
 }
 
 bool TargetX8632::doBranchOpt(Inst *I, const CfgNode *NextNode) {
   if (InstX8632Br *Br = llvm::dyn_cast<InstX8632Br>(I)) {
     return Br->optimizeBranch(NextNode);
   }
   return false;
 }
@@ skipping 2768 matching lines @@
   OperandX8632Mem *Addr = FormMemoryOperand(Ptr, Expected->getType());
   Variable *DesiredReg = legalizeToVar(Desired);
   const bool Locked = true;
   _cmpxchg(Addr, T_eax, DesiredReg, Locked);
   _mov(DestPrev, T_eax);
 }
 
 bool TargetX8632::tryOptimizedCmpxchgCmpBr(Variable *Dest, Operand *PtrToMem,
                                            Operand *Expected,
                                            Operand *Desired) {
-  if (Ctx->getOptLevel() == Opt_m1)
+  if (Ctx->getFlags().getOptLevel() == Opt_m1)
     return false;
   // Peek ahead a few instructions and see how Dest is used.
   // It's very common to have:
   //
   // %x = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* ptr, i32 %expected, ...)
   // [%y_phi = ...] // list of phi stores
   // %p = icmp eq i32 %x, %expected
   // br i1 %p, label %l1, label %l2
   //
   // which we can optimize into:
@@ skipping 1292 matching lines @@
   assert(Type != IceType_i64);
   Variable *Reg = Func->makeVariable(Type);
   if (RegNum == Variable::NoRegister)
     Reg->setWeightInfinite();
   else
     Reg->setRegNum(RegNum);
   return Reg;
 }
 
 void TargetX8632::postLower() {
-  if (Ctx->getOptLevel() == Opt_m1)
+  if (Ctx->getFlags().getOptLevel() == Opt_m1)
     return;
   // Find two-address non-SSA instructions where Dest==Src0, and set
   // the DestNonKillable flag to keep liveness analysis consistent.
   for (auto Inst = Context.getCur(), E = Context.getNext(); Inst != E; ++Inst) {
     if (Inst->isDeleted())
       continue;
     if (Variable *Dest = Inst->getDest()) {
       // TODO(stichnot): We may need to consider all source
       // operands, not just the first one, if using 3-address
       // instructions.
@@ skipping 294 matching lines @@
   case FT_Asm:
   case FT_Iasm: {
     OstreamLocker L(Ctx);
     emitConstantPool<PoolTypeConverter<float>>(Ctx);
     emitConstantPool<PoolTypeConverter<double>>(Ctx);
   } break;
   }
 }
 
 } // end of namespace Ice