Move some flag-like props from GlobalContext and TargetLowering to ClFlags.

src/IceTargetLowering.cpp

 //===- subzero/src/IceTargetLowering.cpp - Basic lowering implementation --===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the skeleton of the TargetLowering class,
 // specifically invoking the appropriate lowering method for a given
 // instruction kind and driving global register allocation.  It also
 // implements the non-deleted instruction iteration in
 // LoweringContext.
 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/Support/CommandLine.h"
-
 #include "assembler_ia32.h"
 #include "IceCfg.h" // setError()
 #include "IceCfgNode.h"
 #include "IceOperand.h"
 #include "IceRegAlloc.h"
 #include "IceTargetLowering.h"
 #include "IceTargetLoweringX8632.h"
 
 namespace Ice {
 
-namespace {
-
-// TODO(stichnot): Move this machinery into main.cpp.
-namespace cl = llvm::cl;
-cl::opt<bool> DoNopInsertion("nop-insertion", cl::desc("Randomly insert NOPs"),
-                             cl::init(false));
-
-cl::opt<int> MaxNopsPerInstruction(
-    "max-nops-per-instruction",
-    cl::desc("Max number of nops to insert per instruction"), cl::init(1));
-
-cl::opt<int> NopProbabilityAsPercentage(
-    "nop-insertion-percentage",
-    cl::desc("Nop insertion probability as percentage"), cl::init(10));
-
-cl::opt<bool>
-    CLRandomizeRegisterAllocation("randomize-regalloc",
-                                  cl::desc("Randomize register allocation"),
-                                  cl::init(false));
-} // end of anonymous namespace
-
 void LoweringContext::init(CfgNode *N) {
   Node = N;
   End = getNode()->getInsts().end();
   rewind();
   advanceForward(Next);
 }
 
 void LoweringContext::rewind() {
   Begin = getNode()->getInsts().begin();
   Cur = Begin;
@@ skipping 34 matching lines @@
   if (Target == Target_ARM32)
     return IceTargetARM32::create(Func);
   if (Target == Target_ARM64)
     return IceTargetARM64::create(Func);
 #endif
   Func->setError("Unsupported target");
   return nullptr;
 }
 
 TargetLowering::TargetLowering(Cfg *Func)
-    : Func(Func), Ctx(Func->getContext()),
-      RandomizeRegisterAllocation(CLRandomizeRegisterAllocation),
-      HasComputedFrame(false), CallsReturnsTwice(false), StackAdjustment(0),
-      Context(), SnapshotStackAdjustment(0) {}
+    : Func(Func), Ctx(Func->getContext()), HasComputedFrame(false),
+      CallsReturnsTwice(false), StackAdjustment(0), Context(),
+      SnapshotStackAdjustment(0) {}
 
 std::unique_ptr<Assembler> TargetLowering::createAssembler(TargetArch Target,
                                                            Cfg *Func) {
   // These statements can be #ifdef'd to specialize the assembler
   // to a subset of the available targets.  TODO: use CRTP.
   if (Target == Target_X8632)
     return std::unique_ptr<Assembler>(new x86::AssemblerX86());
   Func->setError("Unsupported target");
   return nullptr;
 }
 
 void TargetLowering::doAddressOpt() {
   if (llvm::isa<InstLoad>(*Context.getCur()))
     doAddressOptLoad();
   else if (llvm::isa<InstStore>(*Context.getCur()))
     doAddressOptStore();
   Context.advanceCur();
   Context.advanceNext();
 }
 
-bool TargetLowering::shouldDoNopInsertion() const { return DoNopInsertion; }
-
 void TargetLowering::doNopInsertion() {
   Inst *I = Context.getCur();
   bool ShouldSkip = llvm::isa<InstFakeUse>(I) || llvm::isa<InstFakeDef>(I) ||
                     llvm::isa<InstFakeKill>(I) || I->isRedundantAssign() ||
                     I->isDeleted();
   if (!ShouldSkip) {
-    for (int I = 0; I < MaxNopsPerInstruction; ++I) {
-      randomlyInsertNop(NopProbabilityAsPercentage / 100.0);
+    int Probability = Ctx->getFlags().getNopProbabilityAsPercentage();
+    for (int I = 0; I < Ctx->getFlags().getMaxNopsPerInstruction(); ++I) {
+      randomlyInsertNop(Probability / 100.0);
     }
   }
 }
 
 // Lowers a single instruction according to the information in
 // Context, by checking the Context.Cur instruction kind and calling
 // the appropriate lowering method.  The lowering method should insert
 // target instructions at the Cur.Next insertion point, and should not
 // delete the Context.Cur instruction or advance Context.Cur.
 //
@@ skipping 95 matching lines @@
   TimerMarker T(TimerStack::TT_regAlloc, Func);
   LinearScan LinearScan(Func);
   RegSetMask RegInclude = RegSet_None;
   RegSetMask RegExclude = RegSet_None;
   RegInclude |= RegSet_CallerSave;
   RegInclude |= RegSet_CalleeSave;
   if (hasFramePointer())
     RegExclude |= RegSet_FramePointer;
   LinearScan.init(Kind);
   llvm::SmallBitVector RegMask = getRegisterSet(RegInclude, RegExclude);
-  LinearScan.scan(RegMask, RandomizeRegisterAllocation);
+  LinearScan.scan(RegMask, Ctx->getFlags().shouldRandomizeRegAlloc());
 }
 
 std::unique_ptr<TargetDataLowering>
 TargetDataLowering::createLowering(GlobalContext *Ctx) {
   // These statements can be #ifdef'd to specialize the code generator
   // to a subset of the available targets.  TODO: use CRTP.
-  TargetArch Target = Ctx->getTargetArch();
+  TargetArch Target = Ctx->getFlags().getTargetArch();
   if (Target == Target_X8632)
     return std::unique_ptr<TargetDataLowering>(TargetDataX8632::create(Ctx));
 #if 0
   if (Target == Target_X8664)
     return std::unique_ptr<TargetDataLowering>(TargetDataX8664::create(Ctx));
   if (Target == Target_ARM32)
     return std::unique_ptr<TargetDataLowering>(TargetDataARM32::create(Ctx));
   if (Target == Target_ARM64)
     return std::unique_ptr<TargetDataLowering>(TargetDataARM64::create(Ctx));
 #endif
   llvm_unreachable("Unsupported target");
   return nullptr;
 }
 
 TargetDataLowering::~TargetDataLowering() {}
 
 } // end of namespace Ice