Subzero: Fix inappropriate use of nullptr.

tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll

 ; This tests each of the supported NaCl atomic instructions for every
 ; size allowed.
 
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
 ; RUN:   | FileCheck %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
 ; RUN:   | FileCheck --check-prefix=O2 %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
 ; RUN:   | FileCheck %s
 
@@ skipping 10 matching lines @@
 declare i32 @llvm.nacl.atomic.rmw.i32(i32, i32*, i32, i32)
 declare i64 @llvm.nacl.atomic.rmw.i64(i32, i64*, i64, i32)
 declare i8 @llvm.nacl.atomic.cmpxchg.i8(i8*, i8, i8, i32, i32)
 declare i16 @llvm.nacl.atomic.cmpxchg.i16(i16*, i16, i16, i32, i32)
 declare i32 @llvm.nacl.atomic.cmpxchg.i32(i32*, i32, i32, i32, i32)
 declare i64 @llvm.nacl.atomic.cmpxchg.i64(i64*, i64, i64, i32, i32)
 declare void @llvm.nacl.atomic.fence(i32)
 declare void @llvm.nacl.atomic.fence.all()
 declare i1 @llvm.nacl.atomic.is.lock.free(i32, i8*)
 
+@Global8 = internal global [1 x i8] zeroinitializer, align 1
+@Global16 = internal global [2 x i8] zeroinitializer, align 2
+@Global32 = internal global [4 x i8] zeroinitializer, align 4
+@Global64 = internal global [8 x i8] zeroinitializer, align 8
+
 ; NOTE: The LLC equivalent for 16-bit atomic operations are expanded
 ; as 32-bit operations. For Subzero, assume that real 16-bit operations
 ; will be usable (the validator will be fixed):
 ; https://code.google.com/p/nativeclient/issues/detail?id=2981
 
 ;;; Load
 
 ; x86 guarantees load/store to be atomic if naturally aligned.
 ; The PNaCl IR requires all atomic accesses to be naturally aligned.
 
@@ skipping 195 matching lines @@
 ; clobbered in the loop, and the RHS needs to be remain live.
 ; CHECK: add ebx,{{.*e.[^x]}}
 ; CHECK: mov ecx,edx
 ; CHECK: adc ecx,{{.*e.[^x]}}
 ; Ptr cannot be eax, ebx, ecx, or edx (used up for the expected and desired).
 ; It can be esi, edi, or ebp though, for example (so we need to be careful
 ; about rejecting eb* and ed*.)
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
 ; CHECK: jne [[LABEL]]
 
+; Same test as above, but with a global address to test FakeUse issues.
+define i64 @test_atomic_rmw_add_64_global(i64 %v) {
+entry:
+  %ptr = bitcast [8 x i8]* @Global64 to i64*
+  %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr, i64 %v, i32 6)
+  ret i64 %a
+}
+; CHECK-LABEL: test_atomic_rmw_add_64_global
+
 ; Test with some more register pressure. When we have an alloca, ebp is
 ; used to manage the stack frame, so it cannot be used as a register either.
 declare void @use_ptr(i32 %iptr)
 
 define i64 @test_atomic_rmw_add_64_alloca(i32 %iptr, i64 %v) {
 entry:
   %alloca_ptr = alloca i8, i32 16, align 16
   %ptr = inttoptr i32 %iptr to i64*
   %old = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr, i64 %v, i32 6)
   store i8 0, i8* %alloca_ptr, align 1
@@ skipping 139 matching lines @@
   ret i32 %a_ext
 }
 ; CHECK-LABEL: test_atomic_rmw_or_8
 ; CHECK: mov al,BYTE PTR
 ; Dest cannot be eax here, because eax is used for the old value. Also want
 ; to make sure that cmpxchg's source is the same register.
 ; CHECK: or [[REG:[^a].]]
 ; CHECK: lock cmpxchg BYTE PTR [e{{[^a].}}],[[REG]]
 ; CHECK: jne
 
+; Same test as above, but with a global address to test FakeUse issues.
+define i32 @test_atomic_rmw_or_8_global(i32 %v) {
+entry:
+  %trunc = trunc i32 %v to i8
+  %ptr = bitcast [1 x i8]* @Global8 to i8*
+  %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 3, i8* %ptr, i8 %trunc, i32 6)
+  %a_ext = zext i8 %a to i32
+  ret i32 %a_ext
+}
+; CHECK-LABEL: test_atomic_rmw_or_8_global
+
 define i32 @test_atomic_rmw_or_16(i32 %iptr, i32 %v) {
 entry:
   %trunc = trunc i32 %v to i16
   %ptr = inttoptr i32 %iptr to i16*
   %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 3, i16* %ptr, i16 %trunc, i32 6)
   %a_ext = zext i16 %a to i32
   ret i32 %a_ext
 }
 ; CHECK-LABEL: test_atomic_rmw_or_16
 ; CHECK: mov ax,WORD PTR
 ; CHECK: or [[REG:[^a].]]
 ; CHECK: lock cmpxchg WORD PTR [e{{[^a].}}],[[REG]]
 ; CHECK: jne
 
+; Same test as above, but with a global address to test FakeUse issues.
+define i32 @test_atomic_rmw_or_16_global(i32 %v) {
+entry:
+  %trunc = trunc i32 %v to i16
+  %ptr = bitcast [2 x i8]* @Global16 to i16*
+  %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 3, i16* %ptr, i16 %trunc, i32 6)
+  %a_ext = zext i16 %a to i32
+  ret i32 %a_ext
+}
+; CHECK-LABEL: test_atomic_rmw_or_16_global
+
 define i32 @test_atomic_rmw_or_32(i32 %iptr, i32 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32* %ptr, i32 %v, i32 6)
   ret i32 %a
 }
 ; CHECK-LABEL: test_atomic_rmw_or_32
 ; CHECK: mov eax,DWORD PTR
 ; CHECK: or [[REG:e[^a].]]
 ; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}],[[REG]]
 ; CHECK: jne
 
+; Same test as above, but with a global address to test FakeUse issues.
+define i32 @test_atomic_rmw_or_32_global(i32 %v) {
+entry:
+  %ptr = bitcast [4 x i8]* @Global32 to i32*
+  %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32* %ptr, i32 %v, i32 6)
+  ret i32 %a
+}
+; CHECK-LABEL: test_atomic_rmw_or_32_global
+
 define i64 @test_atomic_rmw_or_64(i32 %iptr, i64 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 3, i64* %ptr, i64 %v, i32 6)
   ret i64 %a
 }
 ; CHECK-LABEL: test_atomic_rmw_or_64
 ; CHECK: push ebx
 ; CHECK: mov eax,DWORD PTR [{{.*}}]
 ; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
@@ skipping 426 matching lines @@
 
 not_lock_free:
   %z = add i32 %x, %y
   ret i32 %z
 }
 ; CHECK-LABEL: test_atomic_is_lock_free_can_dce
 ; CHECK: mov {{.*}},0x1
 ; CHECK: ret
 ; CHECK: add
 ; CHECK: ret