Subzero: Add fabs intrinsic support.

src/IceInstX8632.cpp

 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the InstX8632 and OperandX8632 classes,
@@ skipping 925 matching lines @@
 template <> const char *InstX8632Div::Opcode = "div";
 template <> const char *InstX8632Divps::Opcode = "divps";
 template <> const char *InstX8632Idiv::Opcode = "idiv";
 template <> const char *InstX8632Divss::Opcode = "divss";
 template <> const char *InstX8632Rol::Opcode = "rol";
 template <> const char *InstX8632Shl::Opcode = "shl";
 template <> const char *InstX8632Psll::Opcode = "psll";
 template <> const char *InstX8632Shr::Opcode = "shr";
 template <> const char *InstX8632Sar::Opcode = "sar";
 template <> const char *InstX8632Psra::Opcode = "psra";
+template <> const char *InstX8632Psrl::Opcode = "psrl";
 template <> const char *InstX8632Pcmpeq::Opcode = "pcmpeq";
 template <> const char *InstX8632Pcmpgt::Opcode = "pcmpgt";
 template <> const char *InstX8632MovssRegs::Opcode = "movss";
 // Ternary ops
 template <> const char *InstX8632Insertps::Opcode = "insertps";
 template <> const char *InstX8632Shufps::Opcode = "shufps";
 template <> const char *InstX8632Pinsr::Opcode = "pinsr";
 template <> const char *InstX8632Blendvps::Opcode = "blendvps";
 template <> const char *InstX8632Pblendvb::Opcode = "pblendvb";
 // Three address ops
@@ skipping 127 matching lines @@
 
 // Binary XMM Shift ops
 template <>
 const x86::AssemblerX86::XmmEmitterShiftOp InstX8632Psll::Emitter = {
     &x86::AssemblerX86::psll, &x86::AssemblerX86::psll,
     &x86::AssemblerX86::psll};
 template <>
 const x86::AssemblerX86::XmmEmitterShiftOp InstX8632Psra::Emitter = {
     &x86::AssemblerX86::psra, &x86::AssemblerX86::psra,
     &x86::AssemblerX86::psra};
+template <>
+const x86::AssemblerX86::XmmEmitterShiftOp InstX8632Psrl::Emitter = {
+    &x86::AssemblerX86::psrl, &x86::AssemblerX86::psrl,
+    &x86::AssemblerX86::psrl};
 
 template <> void InstX8632Sqrtss::emit(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Type Ty = getSrc(0)->getType();
   assert(isScalarFloatingType(Ty));
   Str << "\tsqrt" << TypeX8632Attributes[Ty].SdSsString << "\t";
   getSrc(0)->emit(Func);
@@ skipping 1569 matching lines @@
   assert(getDest()->getType() == IceType_v8i16 ||
          getDest()->getType() == IceType_v8i1 ||
          getDest()->getType() == IceType_v4i32 ||
          getDest()->getType() == IceType_v4i1);
   char buf[30];
   snprintf(buf, llvm::array_lengthof(buf), "psra%s",
            TypeX8632Attributes[getDest()->getType()].PackString);
   emitTwoAddress(buf, this, Func);
 }
 
+template <> void InstX8632Psrl::emit(const Cfg *Func) const {
+  if (!ALLOW_DUMP)
+    return;
+  char buf[30];
+  snprintf(buf, llvm::array_lengthof(buf), "psrl%s",
+           TypeX8632Attributes[getDest()->getType()].PackString);
+  emitTwoAddress(buf, this, Func);
+}
+
 void InstX8632Ret::emit(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "\tret";
 }
 
 void InstX8632Ret::emitIAS(const Cfg *Func) const {
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   Asm->ret();
@@ skipping 244 matching lines @@
   }
   Str << "(";
   if (Func)
     Var->dump(Func);
   else
     Var->dump(Str);
   Str << ")";
 }
 
 } // end of namespace Ice