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Unified Diff: src/compiler/arm64/instruction-codes-arm64.h

Issue 1021533002: [ARM64] [turbofan] Support uxtb/uxth for add/sub. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Small fix. Created 5 years, 9 months ago
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Index: src/compiler/arm64/instruction-codes-arm64.h
diff --git a/src/compiler/arm64/instruction-codes-arm64.h b/src/compiler/arm64/instruction-codes-arm64.h
index 242d25d0093440dbdfd77c8b4b53e26ddec610d9..dfd90da44aad0a562aabac8c95000376432cd49f 100644
--- a/src/compiler/arm64/instruction-codes-arm64.h
+++ b/src/compiler/arm64/instruction-codes-arm64.h
@@ -130,13 +130,15 @@ namespace compiler {
// I = immediate (handle, external, int32)
// MRI = [register + immediate]
// MRR = [register + register]
-#define TARGET_ADDRESSING_MODE_LIST(V) \
- V(MRI) /* [%r0 + K] */ \
- V(MRR) /* [%r0 + %r1] */ \
- V(Operand2_R_LSL_I) /* %r0 LSL K */ \
- V(Operand2_R_LSR_I) /* %r0 LSR K */ \
- V(Operand2_R_ASR_I) /* %r0 ASR K */ \
- V(Operand2_R_ROR_I) /* %r0 ROR K */
+#define TARGET_ADDRESSING_MODE_LIST(V) \
+ V(MRI) /* [%r0 + K] */ \
+ V(MRR) /* [%r0 + %r1] */ \
+ V(Operand2_R_LSL_I) /* %r0 LSL K */ \
+ V(Operand2_R_LSR_I) /* %r0 LSR K */ \
+ V(Operand2_R_ASR_I) /* %r0 ASR K */ \
+ V(Operand2_R_ROR_I) /* %r0 ROR K */ \
+ V(Operand2_R_UXTB) /* %r0 UXTB (unsigned extend byte) */ \
+ V(Operand2_R_UXTH) /* %r0 UXTH (unsigned extend halfword) */
} // namespace internal
} // namespace compiler
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