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Side by Side Diff: src/compiler/arm64/instruction-codes-arm64.h

Issue 1021183002: [turbofan] Turn Math.clz32 into an inlinable builtin. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 9 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
11 11
12 // ARM64-specific opcodes that specify which assembly sequence to emit. 12 // ARM64-specific opcodes that specify which assembly sequence to emit.
13 // Most opcodes specify a single instruction. 13 // Most opcodes specify a single instruction.
14 #define TARGET_ARCH_OPCODE_LIST(V) \ 14 #define TARGET_ARCH_OPCODE_LIST(V) \
15 V(Arm64Add) \ 15 V(Arm64Add) \
16 V(Arm64Add32) \ 16 V(Arm64Add32) \
17 V(Arm64And) \ 17 V(Arm64And) \
18 V(Arm64And32) \ 18 V(Arm64And32) \
19 V(Arm64Bic) \ 19 V(Arm64Bic) \
20 V(Arm64Bic32) \ 20 V(Arm64Bic32) \
21 V(Arm64Clz32) \
21 V(Arm64Cmp) \ 22 V(Arm64Cmp) \
22 V(Arm64Cmp32) \ 23 V(Arm64Cmp32) \
23 V(Arm64Cmn) \ 24 V(Arm64Cmn) \
24 V(Arm64Cmn32) \ 25 V(Arm64Cmn32) \
25 V(Arm64Tst) \ 26 V(Arm64Tst) \
26 V(Arm64Tst32) \ 27 V(Arm64Tst32) \
27 V(Arm64Or) \ 28 V(Arm64Or) \
28 V(Arm64Or32) \ 29 V(Arm64Or32) \
29 V(Arm64Orn) \ 30 V(Arm64Orn) \
30 V(Arm64Orn32) \ 31 V(Arm64Orn32) \
(...skipping 107 matching lines...) Expand 10 before | Expand all | Expand 10 after
138 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ 139 V(Operand2_R_ASR_I) /* %r0 ASR K */ \
139 V(Operand2_R_ROR_I) /* %r0 ROR K */ \ 140 V(Operand2_R_ROR_I) /* %r0 ROR K */ \
140 V(Operand2_R_UXTB) /* %r0 UXTB (unsigned extend byte) */ \ 141 V(Operand2_R_UXTB) /* %r0 UXTB (unsigned extend byte) */ \
141 V(Operand2_R_UXTH) /* %r0 UXTH (unsigned extend halfword) */ 142 V(Operand2_R_UXTH) /* %r0 UXTH (unsigned extend halfword) */
142 143
143 } // namespace internal 144 } // namespace internal
144 } // namespace compiler 145 } // namespace compiler
145 } // namespace v8 146 } // namespace v8
146 147
147 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 148 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
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