Subzero: Support non sequentially consistent memory orderings for atomic ops.

src/IceTargetLoweringX8632.cpp

Index: src/IceTargetLoweringX8632.cpp
diff --git a/src/IceTargetLoweringX8632.cpp b/src/IceTargetLoweringX8632.cpp
index ebfc4d2da1ea6eaa5e0d5f728ad959b13808bc90..a49927ed4752eff84caca43c9089b2c792b1b032 100644
--- a/src/IceTargetLoweringX8632.cpp
+++ b/src/IceTargetLoweringX8632.cpp
@@ -2857,16 +2857,12 @@ void TargetX8632::lowerInsertElement(const InstInsertElement *Inst) {
 }
 
 void TargetX8632::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
-  switch (Instr->getIntrinsicInfo().ID) {
+  switch (Intrinsics::IntrinsicID ID = Instr->getIntrinsicInfo().ID) {
   case Intrinsics::AtomicCmpxchg: {
-    if (!Intrinsics::VerifyMemoryOrder(
-            llvm::cast<ConstantInteger32>(Instr->getArg(3))->getValue())) {
-      Func->setError("Unexpected memory ordering (success) for AtomicCmpxchg");
-      return;
-    }
-    if (!Intrinsics::VerifyMemoryOrder(
+    if (!Intrinsics::isMemoryOrderValid(
+            ID, llvm::cast<ConstantInteger32>(Instr->getArg(3))->getValue(),
             llvm::cast<ConstantInteger32>(Instr->getArg(4))->getValue())) {
-      Func->setError("Unexpected memory ordering (failure) for AtomicCmpxchg");
+      Func->setError("Unexpected memory ordering for AtomicCmpxchg");
       return;
     }
     Variable *DestPrev = Instr->getDest();
@@ -2879,8 +2875,8 @@ void TargetX8632::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
     return;
   }
   case Intrinsics::AtomicFence:
-    if (!Intrinsics::VerifyMemoryOrder(
-            llvm::cast<ConstantInteger32>(Instr->getArg(0))->getValue())) {
+    if (!Intrinsics::isMemoryOrderValid(
+            ID, llvm::cast<ConstantInteger32>(Instr->getArg(0))->getValue())) {
       Func->setError("Unexpected memory ordering for AtomicFence");
       return;
     }
@@ -2925,8 +2921,8 @@ void TargetX8632::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
   case Intrinsics::AtomicLoad: {
     // We require the memory address to be naturally aligned.
     // Given that is the case, then normal loads are atomic.
-    if (!Intrinsics::VerifyMemoryOrder(
-            llvm::cast<ConstantInteger32>(Instr->getArg(1))->getValue())) {
+    if (!Intrinsics::isMemoryOrderValid(
+            ID, llvm::cast<ConstantInteger32>(Instr->getArg(1))->getValue())) {
       Func->setError("Unexpected memory ordering for AtomicLoad");
       return;
     }
@@ -2958,8 +2954,8 @@ void TargetX8632::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
     return;
   }
   case Intrinsics::AtomicRMW:
-    if (!Intrinsics::VerifyMemoryOrder(
-            llvm::cast<ConstantInteger32>(Instr->getArg(3))->getValue())) {
+    if (!Intrinsics::isMemoryOrderValid(
+            ID, llvm::cast<ConstantInteger32>(Instr->getArg(3))->getValue())) {
       Func->setError("Unexpected memory ordering for AtomicRMW");
       return;
     }
@@ -2969,8 +2965,8 @@ void TargetX8632::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
                    Instr->getArg(1), Instr->getArg(2));
     return;
   case Intrinsics::AtomicStore: {
-    if (!Intrinsics::VerifyMemoryOrder(
-            llvm::cast<ConstantInteger32>(Instr->getArg(2))->getValue())) {
+    if (!Intrinsics::isMemoryOrderValid(
+            ID, llvm::cast<ConstantInteger32>(Instr->getArg(2))->getValue())) {
       Func->setError("Unexpected memory ordering for AtomicStore");
       return;
     }