Subzero: Support non sequentially consistent memory orderings for atomic ops.

tests_lit/llvm2ice_tests/nacl-atomic-errors.ll

Index: tests_lit/llvm2ice_tests/nacl-atomic-errors.ll
diff --git a/tests_lit/llvm2ice_tests/nacl-atomic-errors.ll b/tests_lit/llvm2ice_tests/nacl-atomic-errors.ll
index 92de7aac5fa8c50cabbdfa0259c88221fe5562e0..6e587288eca0e001aa10851327db3e7d127292b3 100644
--- a/tests_lit/llvm2ice_tests/nacl-atomic-errors.ll
+++ b/tests_lit/llvm2ice_tests/nacl-atomic-errors.ll
@@ -19,8 +19,8 @@ declare void @llvm.nacl.atomic.fence(i32)
 declare i1 @llvm.nacl.atomic.is.lock.free(i32, i8*)
 
 ;;; Load
-;;; Check unexpected memory order parameter (only sequential
-;;; consistency == 6 is currently allowed).
+;;; Check unexpected memory order parameter (release=4 and acq_rel=5
+;;; are disallowed).
 
 define i32 @error_atomic_load_8(i32 %iptr) {
 entry:
@@ -34,7 +34,7 @@ entry:
 define i32 @error_atomic_load_16(i32 %iptr) {
 entry:
   %ptr = inttoptr i32 %iptr to i16*
-  %i = call i16 @llvm.nacl.atomic.load.i16(i16* %ptr, i32 1)
+  %i = call i16 @llvm.nacl.atomic.load.i16(i16* %ptr, i32 4)
   %r = zext i16 %i to i32
   ret i32 %r
 }
@@ -43,13 +43,14 @@ entry:
 define i64 @error_atomic_load_64(i32 %iptr) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
-  %r = call i64 @llvm.nacl.atomic.load.i64(i64* %ptr, i32 2)
+  %r = call i64 @llvm.nacl.atomic.load.i64(i64* %ptr, i32 5)
   ret i64 %r
 }
 ; CHECK: Unexpected memory ordering for AtomicLoad
 
 
 ;;; Store
+;;; consume=2, acquire=3, acq_rel=5 are disallowed
 
 define void @error_atomic_store_32(i32 %iptr, i32 %v) {
 entry:
@@ -70,19 +71,20 @@ entry:
 define void @error_atomic_store_64_const(i32 %iptr) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
-  call void @llvm.nacl.atomic.store.i64(i64 12345678901234, i64* %ptr, i32 4)
+  call void @llvm.nacl.atomic.store.i64(i64 12345678901234, i64* %ptr, i32 5)
   ret void
 }
 ; CHECK: Unexpected memory ordering for AtomicStore
 
 ;;; RMW
 ;;; Test atomic memory order and operation.
+;;; Modes 3:6 allowed.
 
 define i32 @error_atomic_rmw_add_8(i32 %iptr, i32 %v) {
 entry:
   %trunc = trunc i32 %v to i8
   %ptr = inttoptr i32 %iptr to i8*
-  %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 1, i8* %ptr, i8 %trunc, i32 5)
+  %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 1, i8* %ptr, i8 %trunc, i32 1)
   %a_ext = zext i8 %a to i32
   ret i32 %a_ext
 }
@@ -91,7 +93,7 @@ entry:
 define i64 @error_atomic_rmw_add_64(i32 %iptr, i64 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
-  %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr, i64 %v, i32 4)
+  %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr, i64 %v, i32 7)
   ret i64 %a
 }
 ; CHECK: Unexpected memory ordering for AtomicRMW
@@ -131,7 +133,7 @@ entry:
                                                i32 %desired, i32 0, i32 6)
   ret i32 %old
 }
-; CHECK: Unexpected memory ordering (success) for AtomicCmpxchg
+; CHECK: Unexpected memory ordering for AtomicCmpxchg
 
 define i32 @error_atomic_cmpxchg_32_failure(i32 %iptr, i32 %expected, i32 %desired) {
 entry:
@@ -140,22 +142,22 @@ entry:
                                                i32 %desired, i32 6, i32 0)
   ret i32 %old
 }
-; CHECK: Unexpected memory ordering (failure) for AtomicCmpxchg
+; CHECK: Unexpected memory ordering for AtomicCmpxchg
 
 define i64 @error_atomic_cmpxchg_64_failure(i32 %iptr, i64 %expected, i64 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
-                                               i64 %desired, i32 6, i32 3)
+                                               i64 %desired, i32 4, i32 1)
   ret i64 %old
 }
-; CHECK: Unexpected memory ordering (failure) for AtomicCmpxchg
+; CHECK: Unexpected memory ordering for AtomicCmpxchg
 
 ;;; Fence and is-lock-free.
 
 define void @error_atomic_fence() {
 entry:
-  call void @llvm.nacl.atomic.fence(i32 1)
+  call void @llvm.nacl.atomic.fence(i32 0)
   ret void
 }
 ; CHECK: Unexpected memory ordering for AtomicFence
@@ -168,3 +170,58 @@ entry:
   ret i32 %r
 }
 ; CHECK: AtomicIsLockFree byte size should be compile-time const
+
+
+;;; Test bad non-constant memory ordering values.
+
+define i32 @error_atomic_load_8_nonconst(i32 %iptr) {
+entry:
+  %ptr = inttoptr i32 %iptr to i8*
+  %i = call i8 @llvm.nacl.atomic.load.i8(i8* %ptr, i32 %iptr)
+  %r = zext i8 %i to i32
+  ret i32 %r
+}
+; CHECK: Unexpected memory ordering for AtomicLoad
+
+define void @error_atomic_store_32_nonconst(i32 %iptr, i32 %v) {
+entry:
+  %ptr = inttoptr i32 %iptr to i32*
+  call void @llvm.nacl.atomic.store.i32(i32 %v, i32* %ptr, i32 %v)
+  ret void
+}
+; CHECK: Unexpected memory ordering for AtomicStore
+
+define i32 @error_atomic_rmw_add_8_nonconst(i32 %iptr, i32 %v) {
+entry:
+  %trunc = trunc i32 %v to i8
+  %ptr = inttoptr i32 %iptr to i8*
+  %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 1, i8* %ptr, i8 %trunc, i32 %iptr)
+  %a_ext = zext i8 %a to i32
+  ret i32 %a_ext
+}
+; CHECK: Unexpected memory ordering for AtomicRMW
+
+define i32 @error_atomic_cmpxchg_32_success_nonconst_1(i32 %iptr, i32 %expected, i32 %desired) {
+entry:
+  %ptr = inttoptr i32 %iptr to i32*
+  %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
+                                               i32 %desired, i32 %iptr, i32 6)
+  ret i32 %old
+}
+; CHECK: Unexpected memory ordering for AtomicCmpxchg
+
+define i32 @error_atomic_cmpxchg_32_success_nonconst_2(i32 %iptr, i32 %expected, i32 %desired) {
+entry:
+  %ptr = inttoptr i32 %iptr to i32*
+  %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
+                                               i32 %desired, i32 6, i32 %iptr)
+  ret i32 %old
+}
+; CHECK: Unexpected memory ordering for AtomicCmpxchg
+
+define void @error_atomic_fence_nonconst(i32 %v) {
+entry:
+  call void @llvm.nacl.atomic.fence(i32 %v)
+  ret void
+}
+; CHECK: Unexpected memory ordering for AtomicFence