Subzero: Support non sequentially consistent memory orderings for atomic ops.

src/IceIntrinsics.cpp

Index: src/IceIntrinsics.cpp
diff --git a/src/IceIntrinsics.cpp b/src/IceIntrinsics.cpp
index 26a81dea7eaa10b5836e1aac95d29011c9396db9..0620d9cd4e35fcd8c3dbc3f92f242b638def0209 100644
--- a/src/IceIntrinsics.cpp
+++ b/src/IceIntrinsics.cpp
@@ -233,9 +233,59 @@ const Intrinsics::FullIntrinsicInfo *Intrinsics::find(const IceString &Name,
   return &it->second;
 }
 
-bool Intrinsics::VerifyMemoryOrder(uint64_t Order) {
-  // There is only one memory ordering for atomics allowed right now.
-  return Order == Intrinsics::MemoryOrderSequentiallyConsistent;
+bool Intrinsics::isMemoryOrderValid(IntrinsicID ID, uint64_t Order,
+                                    uint64_t OrderOther) {
+  // Reject orderings not allowed in PNaCl.
+  switch (Order) {
+  case Intrinsics::MemoryOrderAcquire:
+  case Intrinsics::MemoryOrderRelease:
+  case Intrinsics::MemoryOrderAcquireRelease:
+  case Intrinsics::MemoryOrderSequentiallyConsistent:
+    break;
+  default:
+    return false;
+  }
+  // Reject orderings not allowed by C++11.
+  switch (ID) {
+  default:
+    llvm_unreachable("isMemoryOrderValid: Unknown IntrinsicID");
+    return false;
+  case AtomicFence:
+  case AtomicFenceAll:
+  case AtomicRMW:
+    return true;
+  case AtomicCmpxchg:
+    // Reject orderings not allowed in PNaCl or that are invalid
+    // combinations for cmpxchg.

[JF, 2015/03/17 21:18:14]

This code should only deal with what's invalid for C++, not PNaCl.

[Jim Stichnoth, 2015/03/18 00:00:25]

Done.

+    switch (OrderOther) {
+    case Intrinsics::MemoryOrderAcquire:
+    case Intrinsics::MemoryOrderSequentiallyConsistent:
+      if (OrderOther > Order)
+        return false;
+      if (Order == Intrinsics::MemoryOrderRelease)
+        return false;
+      return true;
+    default:
+      return false;
+    }
+  case AtomicLoad:
+    switch (Order) {
+    case Intrinsics::MemoryOrderRelease:
+    case Intrinsics::MemoryOrderAcquireRelease:
+      return false;
+    default:
+      return true;
+    }
+  case AtomicStore:
+    switch (Order) {
+    case Intrinsics::MemoryOrderConsume:
+    case Intrinsics::MemoryOrderAcquire:
+    case Intrinsics::MemoryOrderAcquireRelease:
+      return false;
+    default:
+      return true;
+    }
+  }
 }
 
 Intrinsics::ValidateCallValue