Subzero: Support non sequentially consistent memory orderings for atomic ops.

src/IceIntrinsics.cpp

 //===- subzero/src/IceIntrinsics.cpp - Functions related to intrinsics ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the Intrinsics utilities for matching and
@@ skipping 215 matching lines @@
     return nullptr;
   IceString NameSuffix = Name.substr(LLVMPrefixLen);
   auto it = Map.find(NameSuffix);
   if (it == Map.end()) {
     Error = true;
     return nullptr;
   }
   return &it->second;
 }
 
-bool Intrinsics::VerifyMemoryOrder(uint64_t Order) {
-  // There is only one memory ordering for atomics allowed right now.
-  return Order == Intrinsics::MemoryOrderSequentiallyConsistent;
+bool Intrinsics::isMemoryOrderValid(IntrinsicID ID, uint64_t Order,
+                                    uint64_t OrderOther) {
+  // Reject orderings not allowed in PNaCl.
+  switch (Order) {
+  case Intrinsics::MemoryOrderInvalid:
+  case Intrinsics::MemoryOrderNum:
+  case Intrinsics::MemoryOrderRelaxed:
+  case Intrinsics::MemoryOrderConsume:
+    return false;
+  }

[JF, 2015/03/17 16:58:53]

I'd do the opposite and whitelist acquire/release/acq_rel/seq_cst: the file
format could contain any other number and you don't want to let them through.

[Jim Stichnoth, 2015/03/17 18:42:04]

Done.

+  // Reject orderings not allowed by C++11.
+  switch (ID) {
+  default:
+    llvm_unreachable("isMemoryOrderValid: Unknown IntrinsicID");
+    return false;
+  case AtomicFence:
+  case AtomicFenceAll:
+  case AtomicRMW:
+    return true;
+  case AtomicCmpxchg:
+    switch (OrderOther) {
+    case Intrinsics::MemoryOrderInvalid:
+    case Intrinsics::MemoryOrderNum:
+    case Intrinsics::MemoryOrderRelease:
+    case Intrinsics::MemoryOrderAcquireRelease:
+    case Intrinsics::MemoryOrderRelaxed:
+    case Intrinsics::MemoryOrderConsume:
+      return false;
+    default:
+      if (OrderOther > Order)
+        return false;
+      if (Order == Intrinsics::MemoryOrderRelease &&
+          OrderOther != Intrinsics::MemoryOrderRelaxed)

[JF, 2015/03/17 21:18:14]

I would leave this in, otherwise when we add relaxed we won't be doing the right
thing.

[Jim Stichnoth, 2015/03/18 00:00:25]

OK, yeah, that optimization did seem too good to be true...

+        return false;
+      return true;
+    }
+  case AtomicLoad:
+    switch (Order) {
+    case Intrinsics::MemoryOrderRelease:
+    case Intrinsics::MemoryOrderAcquireRelease:
+      return false;
+    default:
+      return true;
+    }
+  case AtomicStore:
+    switch (Order) {
+    case Intrinsics::MemoryOrderConsume:
+    case Intrinsics::MemoryOrderAcquire:
+    case Intrinsics::MemoryOrderAcquireRelease:
+      return false;
+    default:
+      return true;
+    }
+  }
 }
 
 Intrinsics::ValidateCallValue
 Intrinsics::FullIntrinsicInfo::validateCall(const Ice::InstCall *Call,
                                             SizeT &ArgIndex) const {
   assert(NumTypes >= 1);
   Variable *Result = Call->getDest();
   if (Result == nullptr) {
     if (Signature[0] != Ice::IceType_void)
       return Intrinsics::BadReturnType;
@@ skipping 12 matching lines @@
   return Intrinsics::IsValidCall;
 }
 
 Type Intrinsics::FullIntrinsicInfo::getArgType(SizeT Index) const {
   assert(NumTypes > 1);
   assert(Index + 1 < NumTypes);
   return Signature[Index + 1];
 }
 
 } // end of namespace Ice