Subzero: Support non sequentially consistent memory orderings for atomic ops.

src/IceIntrinsics.cpp

 //===- subzero/src/IceIntrinsics.cpp - Functions related to intrinsics ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the Intrinsics utilities for matching and
@@ skipping 215 matching lines @@
     return nullptr;
   IceString NameSuffix = Name.substr(LLVMPrefixLen);
   auto it = Map.find(NameSuffix);
   if (it == Map.end()) {
     Error = true;
     return nullptr;
   }
   return &it->second;
 }
 
-bool Intrinsics::VerifyMemoryOrder(uint64_t Order) {
-  // There is only one memory ordering for atomics allowed right now.
-  return Order == Intrinsics::MemoryOrderSequentiallyConsistent;
+namespace {
+
+// Returns whether PNaCl allows the given memory ordering in general.
+bool isMemoryOrderValidPNaCl(uint64_t Order) {
+  switch (Order) {
+  case Intrinsics::MemoryOrderAcquire:
+  case Intrinsics::MemoryOrderRelease:
+  case Intrinsics::MemoryOrderAcquireRelease:
+  case Intrinsics::MemoryOrderSequentiallyConsistent:
+    return true;
+  default:
+    return false;
+  }
+}
+
+} // end of anonymous namespace
+
+bool Intrinsics::isMemoryOrderValid(IntrinsicID ID, uint64_t Order,
+                                    uint64_t OrderOther) {
+  // Reject orderings not allowed in PNaCl.
+  if (!isMemoryOrderValidPNaCl(Order))
+    return false;
+  if (ID == AtomicCmpxchg && !isMemoryOrderValidPNaCl(OrderOther))
+    return false;
+  // Reject orderings not allowed by C++11.
+  switch (ID) {
+  default:
+    llvm_unreachable("isMemoryOrderValid: Unknown IntrinsicID");
+    return false;
+  case AtomicFence:
+  case AtomicFenceAll:
+  case AtomicRMW:
+    return true;
+  case AtomicCmpxchg:
+    // Reject orderings that are invalid combinations for cmpxchg.
+    switch (OrderOther) {
+    case MemoryOrderAcquire:
+    case MemoryOrderSequentiallyConsistent:

[JF, 2015/03/18 06:26:30]

This is wrong, order can also be relaxed or consume. The rule is:

// C++11 [atomics.types.operations.req]: The failure argument shall not be
// release nor acq_rel. The failure argument shall be no stronger than the
// success argument.
// Where the partial ordering is:
//   relaxed < consume < acquire           < acq_rel < seq_cst
//   relaxed <                     release < acq_rel < seq_cst

See:
 
https://codereview.chromium.org/791053006/diff/220001/lib/Analysis/NaCl/PNaCl...

[Jim Stichnoth, 2015/03/18 13:50:15]

But but, that's covered by the isMemoryOrderValidPNaCl(OrderOther) test, and the
comprehensive tests all pass, and...

Oh, OK, separation of PNaCl and C++11 requirements.  Done.

+      if (OrderOther > Order)
+        return false;
+      if (Order == MemoryOrderRelease && OrderOther != MemoryOrderRelaxed)
+        return false;
+      return true;
+    default:
+      return false;
+    }
+  case AtomicLoad:
+    switch (Order) {
+    case MemoryOrderRelease:
+    case MemoryOrderAcquireRelease:
+      return false;
+    default:
+      return true;
+    }
+  case AtomicStore:
+    switch (Order) {
+    case MemoryOrderConsume:
+    case MemoryOrderAcquire:
+    case MemoryOrderAcquireRelease:
+      return false;
+    default:
+      return true;
+    }
+  }
 }
 
 Intrinsics::ValidateCallValue
 Intrinsics::FullIntrinsicInfo::validateCall(const Ice::InstCall *Call,
                                             SizeT &ArgIndex) const {
   assert(NumTypes >= 1);
   Variable *Result = Call->getDest();
   if (Result == nullptr) {
     if (Signature[0] != Ice::IceType_void)
       return Intrinsics::BadReturnType;
@@ skipping 12 matching lines @@
   return Intrinsics::IsValidCall;
 }
 
 Type Intrinsics::FullIntrinsicInfo::getArgType(SizeT Index) const {
   assert(NumTypes > 1);
   assert(Index + 1 < NumTypes);
   return Signature[Index + 1];
 }
 
 } // end of namespace Ice